Semiconductor memory device and method

A semiconductor memory device comprising:

• a bit line;
• a plurality of memory transistors electrically connected to the bit line;
• a source line electrically connected to the memory transistors;
• a word line electrically connected to a gate electrode of one of the memory transistors;
• a voltage generation circuit configured to generate voltages to be applied to the bit line, the source line, and the word line;
• and
• a control circuit configured to control the voltage generation circuit to generate the voltages, wherein
• the control circuit is further configured to:
• upon receipt of a command for erasing data stored in the memory transistors, determine:
• one of program modes that was previously used to write or erase data in the memory transistors based on a distribution pattern of threshold voltages of the memory transistors, and
• one of the program modes to be used to erase the data, and
• control the voltage generation circuit to generate a pre-program voltage to be applied to the word line and an erase voltage to be applied to at least one of the bit line and the source line based on said one of program modes that was previously used and the program mode to be used to erase the data.