Memory device, memory system includimg the memory device, and operating method of the memory system

Abstract

A memory device includes a memory cell array including memory cells, a first voltage selection circuit suitable for supplying one of a high voltage and a low voltage to one end of the memory cell array in response to a flag signal indicating a forward read operation or a reverse read operation in a read mode, a logic value of the flag signal being determined based on read count information, a second voltage selection circuit suitable for supplying the other voltage of the high voltage and the low voltage to the other end of the memory cell array in response to the flag signal in the read mode, and a read circuit coupled to one of the one end and the other end of the memory cell array and reading data stored in a memory cell selected from the memory cells in the read mode.

Dependencies are inferred from the claim text.