Configurable memory device
AssigneeRambus Inc.
InventorTorsten PARTSCH
Life of this patent
Estimating the term…
Abstract
A memory device may be accessed via multiple channels (e.g., 2 channels, 4 channels, etc.). The data widths (i.e., number of data signals) allocated to each channel are configurable such that a given group of data input/output (I/O) signals may be part of a first channel in one configuration, but be part of another channel in a different configuration. Similarly, the memory arrays (e.g., banks, or bank groups) accessed by a given channel may be configurable such that a given memory array is accessed via a first channel in one configuration but is accessed via a different channel in a different configuration. Finally, the data burst length, data burst size, and data transfer clock cycle are configurable.
Claims20
A memory component, comprising:
- a plurality of command/address (CA) interfaces;
- and
- a plurality of data (DQ) interfaces each comprising a plurality of DQ signal groups, the memory component configurable to operate at least two CA interfaces in association with respective sets of DQ signal groups that are non-overlapping sets of DQ signal groups, to form respective memory channels, wherein at least two of the memory channels have different DQ signal widths, at least two of the plurality of DQ signal groups configurable to be operated as part of at least two of the respective memory channels.
A memory component, comprising:
- a first command/address (CA) interface to communicate commands and addresses as part of a first memory channel;
- a second CA interface to communicate commands and addresses as part of a second memory channel;
- and
- a plurality of data (DQ) interfaces each comprising a plurality of DQ signal groups, the memory component configurable to operate a first set of DQ signal groups as part of the first memory channel, the memory component configurable to operate the first set of DQ signal groups as part of the first memory channel, the memory component configurable to operate a second set of DQ signal groups as part of the second memory channel, where the memory component is configurable to have a first number of DQ signals operating as part of the first memory channel and a second number of DQ signals operating as part of the second memory channel where the first number and the second number are not equal, the first set and the second set to be proper subsets of the plurality of DQ signal groups.
A method of operating a memory component, comprising:
- configuring a first set of data (DQ) interface signals to operate as part of a first memory channel, the first set of DQ interface signals configurable to operate as part of a second memory channel;
- configuring a second set of DQ interface signals to operate as part of the second memory channel, the first set and the second set being nonoverlapping sets;
- operating the first memory channel using a first number of DQ interface signals;
- and
- operating the second memory channel using a second number of DQ interface signals, the first number of DQ interface signals and the second number of DQ interface signals being unequal.
Dependencies are inferred from the claim text.