Configurable Partitioning of Write Combine Buffers

Abstract

A processor includes a data buffer, the data buffer being configured as a write-combine buffer. The processor further includes logic circuitry which is configured to perform: receiving, from a further entity, an input data stream for a write operation, wherein the input data stream is received in blocks of data, and partitioning the data buffer into partitions, wherein the partitioning is based on a size of the blocks of data that are received. The logic circuitry is further configured to perform: writing each of the blocks of data to one of the partitions, each block of data being written to a partition of the data buffer based on an address associated with the respective block of data, and for each of the partitions, determining whether to initiate a draining of the respective partition to further memory based on the data that is stored in the respective partition.

Dependencies are inferred from the claim text.