Macro-op fusion for pipelined architectures
AssigneeSiFive, Inc.
InventorsAndrew Waterman, Krste Asanovic, Joshua Smith
Life of this patent
Estimating the term…
Abstract
Systems and methods are disclosed for macro-op fusion in pipelined architectures. For example, some methods include detecting a sequence of macro-ops stored in an instruction decode buffer, the sequence of macro-ops including a first macro-op, followed by one or more intervening macro-ops, followed by a last macro-op; determining a micro-op that is equivalent to the first macro-op combined with the last macro-op; and forwarding the micro-op to one or more execution resource circuitries for execution.
Claims20
An integrated circuit, comprising:
- an instruction decode buffer configured to store one or more macro-op instructions fetched from a memory;
- and
- fusion predictor circuitry coupled to the instruction decode buffer, the fusion predictor circuitry configured to:
- detect, in the instruction decode buffer, a prefix of a potential macro-op fusion sequence, wherein the prefix comprises one or more fetched macro-op instructions;
- determine a prediction of whether it is beneficial to delay execution of the prefix to wait for one or more subsequent macro-op instructions to be fetched;
- and
- output a control signal based on the prediction to cause a processor pipeline to:
- in response to a prediction that it is beneficial to delay, delay execution of the prefix until at least one subsequent macro-op instruction is fetched, or
- in response to a prediction that it is not beneficial to delay, commence execution of the prefix prior to fetching the at least one subsequent macro-op instruction.
A method comprising:
- detecting, in an instruction decode buffer, a prefix of a potential macro-op fusion sequence, wherein the prefix comprises one or more fetched macro-op instructions;
- determining, using a fusion predictor circuitry, a prediction of whether it is beneficial to delay execution of the prefix to wait for one or more subsequent macro-op instructions to be fetched;
- and
- either:
- in response to a prediction that it is beneficial to delay, delaying execution of the prefix until at least one subsequent macro-op instruction is fetched, or
- in response to a prediction that it is not beneficial to delay, commencing execution of the prefix prior to fetching the at least one subsequent macro-op instruction.
A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to manufacture an integrated circuit comprising:
- an instruction decode buffer configured to store one or more macro-op instructions fetched from a memory;
- and
- fusion predictor circuitry coupled to the instruction decode buffer, the fusion predictor circuitry configured to:
- detect, in the instruction decode buffer, a prefix of a potential macro-op fusion sequence, wherein the prefix comprises one or more fetched macro-op instructions;
- determine a prediction of whether it is beneficial to delay execution of the prefix to wait for one or more subsequent macro-op instructions to be fetched;
- and
- output a control signal based on the prediction to cause a processor pipeline to,
- in response to a prediction that it is beneficial to delay, delay execution of the prefix until at least one subsequent macro-op instruction is fetched, or
- in response to a prediction that it is not beneficial to delay, commence execution of the prefix prior to fetching the at least one subsequent macro-op instruction.
Dependencies are inferred from the claim text.