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US 2026/0072468 A1Published application
Skew control circuit for a high-speed clock distribution network and method for operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSubhadeep DATTA, Tamal DAS
Life of this patent
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Abstract
A skew control circuit is provided. The skew control circuit includes at least one current-mode logic (CML) buffer, and an inductor-capacitor (LC) tank connected in series with a tail current source of the at least one CML buffer. The at least one CML buffer filters a skew between complementary input clocks to a high-speed clock distribution network.
Claims12
A skew control circuit comprising:
- at least one current-mode logic (CML) buffer;
- and
- an inductor-capacitor (LC) tank connected in series with a tail current source of the at least one CML buffer,
- wherein the at least one CML buffer is configured to filter a skew between complementary input clocks to a high-speed clock distribution network.
1 more element
A method for controlling skew, the method comprising:
- determining, by a current-mode logic (CML) buffer, a common-mode frequency response of a complementary input clocks of a high speed clock distribution network;
- and
- controlling, by the CML buffer, the skew between the complementary input clocks of the high speed clock distribution network based on strength of the (2n−1)th odd harmonics in the determined common mode frequency response.
Dependencies are inferred from the claim text.