Integrated circuit device with gate anti-type doped region

An integrated circuit (IC) device, comprising:

• a voltage reference circuit comprising:
• a flipped-gate device (FGD) comprising:
• a first P-well region in a substrate;
• first and second N+ source-drain regions in the first P-well region;
• and
• a P+ gate structure disposed over the first P-well region between the first and second N+ source-drain regions in a plan view of the IC device, the P+ gate structure including a first N+ region aligned alongside the first N+ source-drain region in the plan view and a second N+ region aligned alongside the second N+ source-drain region in the plan view;
• and
• a normal gate device (NGD) comprising:
• a second P-well region in the substrate;
• third and fourth N+ source-drain regions in the second P-well region;
• and
• an N+ gate structure disposed over the second P-well region between the third and fourth N+ source-drain regions in the plan view, the N+ gate structure including at least one P+ region extending between the third and fourth N+ source-drain regions in the plan view, wherein the N+ gate structure is electrically connected to the P+ gate structure.

A method, comprising:

• providing a substrate including a P-well region;
• forming a trench in an upper surface of the P-well region;
• forming a dielectric structure in the trench;
• forming a dielectric layer over the P-well region and the dielectric structure;
• forming an N+ gate structure over the dielectric layer;
• and
• forming at least one P+ region in the N+ gate structure, the at least one P+ region located over the P-well region and the dielectric structure.