Semiconductor device including a superlattice providing metal work function tuning

A semiconductor gate-all-around (GAA) device comprising:

• source and drain regions;
• a plurality of semiconductor nanostructures extending between the source and drain regions;
• a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement;
• and
• a first superlattice adjacent at least one of the source and drain regions and comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A semiconductor gate-all-around (GAA) device comprising:

• source and drain regions;
• a plurality of semiconductor nanostructures extending between the source and drain regions;
• a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement;
• a first superlattice adjacent respective portions of the source and drain regions and each comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
• and
• a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A semiconductor gate-all-around (GAA) device comprising:

• source and drain regions;
• a plurality of semiconductor nanostructures extending between the source and drain regions;
• a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement;
• and
• a first superlattice adjacent at least one of the source and drain regions and comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.