Low voltage differential signaling (lvds) system having a built-in self-testing (bist) circuit

A low voltage differential serial (LVDS) communication system, comprising:

• a first system-on-chip (SoC), wherein the first SoC is configured to communication with a second SoC via an LVDS interface, the first SoC comprising:
• a transmitter configured to serially transmit data;
• a receiver configured to serially receive data;
• a first loopback control circuit configured to provide transmitted test data from the transmitter directly to the receiver during testing;
• and
• a built-in self-test (BIST) circuit, configured to perform testing using one of an internal loopback configuration or an external loopback configuration by:
• setting a voltage level of a common mode voltage for the transmitter and the receiver,
• providing a test data pattern for transmission by the transmitter and receiving the test data pattern from the receiver, wherein, when testing using the internal loopback configuration, the loopback control circuit directly provides the transmitted test data pattern to the receiver, and when testing using the external loopback configuration, the test data pattern is transmitted from the transmitter of the first SoC and through a receiver and transmitter of the second SoC prior to receiving the test data pattern at the receiver of the first SoC, and
• determining whether the voltage level of the common mode voltage results in a pass or fail.

In an SoC configured to be used in an LVDS communication system to communicate with a second SoC, a method of performing testing controlled by a built-in self-test (BIST) circuit of the SoC comprises:

• enabling testing in one of an internal loopback configuration or an external loopback configuration;
• setting, by the BIST circuit, an initial voltage level of a common mode voltage for a transmitter and a receiver of the SoC;
• transmitting a test data pattern by the transmitter;
• waiting to receive the test data pattern by the receiver;
• and
• when the test pattern is received by the receiver, determining by the BIST circuit whether the received test pattern matches the test data pattern provided to the transmitter to determine whether the voltage level of the common mode voltage results in a pass or fail,
• wherein, when the testing is enabled in the internal loopback configuration, the test data pattern transmitted by the transmitter is provided directly to the receiver of the SoC, and when testing is enabled in the external loopback configuration, the test data pattern is transmitted from the transmitter of the SoC through a receiver and transmitter of the second SoC prior to receiving the test data pattern at the receiver of the SoC.