Low-power low-area deadtime generator

Abstract

A deadtime generator configured to output a pair of non-overlapping clock signals. A circuit is provide that includes an input node for receiving a clock signal; a first signal path coupled to the input node and having a first output node for outputting a first modified clock signal, wherein the first signal path includes a feedback node coupled to an input of a feedback inverter; a second signal path coupled to the input node and having a second output node for outputting a second modified clock signal, wherein second signal path includes a Low-to-High skewed inverter; and a feedback signal path coupled to second signal path and having a High-to-Low skewed inverter with an output coupled to a gate of at least one transistor, wherein an output of the at least one transistor is coupled to the feedback node.

Dependencies are inferred from the claim text.