Time delay unit for high frequency applications
AssigneeQorvo US, Inc.
InventorCharles Forrest Campbell
Life of this patent
Estimating the term…
Abstract
A time delay circuit includes a first port, a second port, a reference path coupled between the first and second ports, a delay path coupled between the first and second ports, and a control circuit configured to activate one of the reference path and the delay path. The reference path includes a series transistor and a first inductor connected in parallel with the series transistor. The delay path includes a first shunt transistor, a second inductor connected in parallel with the first shunt transistor, and a first impedance inverter coupled between the first port and the first shunt transistor.
Claims20
A time delay circuit, comprising:
- a first port and a second port;
- a reference path coupled between the first and second ports, the reference path including a series transistor and a first inductor connected in parallel with the series transistor;
- a delay path coupled between the first and second ports, the delay path including a first shunt transistor, a second inductor connected in parallel with the first shunt transistor, and a first impedance inverter coupled between the first port and the first shunt transistor;
- and
- a control circuit configured to activate one of the reference path and the delay path.
A multi-bit time delay circuit, comprising:
- a first stage, the first stage including a first reference path and a first delay path, wherein the first reference path includes a first series transistor and a first inductor configured to resonate with an off-state capacitance of the first series transistor, and the first delay path includes a first shunt transistor, a second inductor configured to resonate with an off-state capacitance of the first shunt transistor, and a first impedance inverter connected to the first shunt transistor;
- and
- a second stage cascaded with the first stage, the second stage including a second reference path and a second delay path, wherein the second reference path includes a second series transistor and a third inductor configured to resonate with an off-state capacitance of the second series transistor, and the second delay path includes a second shunt transistor, a fourth inductor configured to resonate with an off-state capacitance of the second shunt transistor, and a second impedance inverter connected to the second shunt transistor.
Dependencies are inferred from the claim text.