# US 2026/0066646 A1 · Electrostatic discharge (esd) protection circuit using tie-cell technique

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2026/0066646 A1
- Document ID: US20260066646A1
- Status: Published application
- Kind: A1
- Application number: 18/823,739
- Filed: 2024-09-04
- Published: 2026-03-05
- Earliest claimed: 2024-09-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: TAO-YI HUNG; JAM-WEM LEE; WUN-JIE LIN; KUO-JI CHEN
- Web page: https://patentgrep.com/patent/US20260066646A1

## CPC

- H02H 9/045: {adapted to a particular application and not provided for elsewhere}
- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H03K 17/687: the devices being field-effect transistors
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The present disclosure provides an integrated circuit, which includes internal circuitry; a pre-driver, a switch device, a post-driver, and an I/O pad. The internal circuitry is configured to generate an input/output (I/O) signal. The pre-driver is configured to generate a first voltage signal based on the I/O signal. The switch device is coupled to the pre-driver. The post-driver is configured to convert the first voltage signal to a second voltage signal. The I/O pad is coupled to the post-driver, and configured to receive the second voltage signal. The switch device is activatable to electrically connect the internal circuitry to the post-driver when the integrated circuit is in a normal operation mode. The switch device is deactivatable to isolate the pre-driver from the post-driver when the integrated circuit is in an electrostatic discharge (ESD) mode and an ESD event occurs on the I/O pad.

## Claims

### Claim 1

An integrated circuit, comprising:
internal circuitry, configured to generate an input/output (I/O) signal;
a pre-driver, coupled to the internal circuitry, configured to generate a first voltage signal based on the I/O signal;
a switch device, coupled to the pre-driver;
a post-driver, configured to convert the first voltage signal to a second voltage signal; and
an I/O pad, coupled to the post-driver, and configured to receive the second voltage signal,
wherein the switch device is activatable to electrically connect the pre-driver to the post-driver when the integrated circuit is in a normal operation mode,
wherein the switch device is deactivatable to isolate the pre-driver from the post-driver when the integrated circuit is in an electrostatic discharge (ESD) mode and an ESD event occurs on the I/O pad.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein:
the first voltage signal is within a first voltage domain between a first power supply voltage and a reference voltage;
the second voltage signal is within a second voltage domain between a second power supply voltage and the reference voltage; and
the second power supply voltage is higher than the first power supply voltage.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the switch device comprises:
a first switch, coupled between a first node and a second node, and configured to receive a first control signal; and
a second switch, coupled between the first node and the second node, and configured to receive a second control signal.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein when the integrated circuit is in the normal operation mode, the first control signal and the second control signal are in a first logic state and a second logic state to turn on the first switch and the second switch, respectively.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, wherein when the integrated circuit is in the ESD mode and the ESD occurs on the I/O pad, the first control signal and the second control signal are in the second logic state and the first logic state to turn off the first switch and the second switch, respectively.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein the post-driver comprises:
a voltage pull-up section, coupled between a first voltage supply node and the I/O pad; and
a voltage pull-down section, coupled between the I/O pad and a reference voltage supply node.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, further comprising:
a first diode, coupled between the first voltage supply node and the I/O pad; and
a second diode, coupled between the I/O pad and the reference voltage supply node.

### Claim 8 (depends on 6)

The integrated circuit of claim 6, wherein:
the first node is coupled to the pre-driver;
the second node is coupled to a gate terminal of a victim transistor within the voltage pull-up section of the post-driver; and
a first terminal of the victim transistor is coupled to the I/O pad and the voltage pull-down section.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the gate terminal of the victim transistor is floating when the switch device is deactivated.

### Claim 10 (depends on 6)

The integrated circuit of claim 6, further comprising:
a detection circuit, configured to generate the first control signal in the first logic state and the second control signal in the second logic state when the integrated circuit is in the normal operation mode, and generate the first control signal in the second logic state and the second control signal in the first logic state when the integrated circuit is in the ESD mode and the ESD event occurs on the I/O pad; and
an ESD power clamp, coupled between the first voltage supply node and the reference voltage supply node.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the detection circuit comprises:
a first transistor, having a gate terminal coupled to a third node, a first terminal coupled to the first voltage supply node, and a second terminal coupled to a fourth node;
a first capacitor, coupled between the first voltage supply node and the third node;
a second transistor, having a gate terminal coupled to the fourth node, a first terminal coupled to the third node, and a second terminal coupled to the reference voltage supply node; and
a second capacitor, coupled between the fourth node and the reference voltage supply node.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the first control signal and the second control signal are generated at the third node and the fourth node.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, wherein the detection circuit further comprises:
a first inverter chain, coupled to the third node, and comprising a first number of inverters connected in series; and
a second inverter chain, coupled to the fourth node, and comprising the first number of inverters connected in series.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein the first control signal and the second control signal are generated at a first point within the first inverter chain and a second point within the second inverter chain, respectively, and the first point and the second point have an equal number of inverters.

### Claim 15

An integrated circuit, comprising:
internal circuitry;
a pre-driver, coupled between a first voltage supply node, a reference voltage supply node, and the internal circuitry;
a switch device, coupled to the pre-driver;
a post-driver, coupled between a second voltage supply node and the reference voltage supply node, and coupled to the pre-driver through the switch device;
an I/O pad, coupled to the post-driver; and
a detection circuit, coupled between the second voltage supply node and the reference voltage supply node, and configured to generate a first control signal and a second control signal,
wherein the first control signal and the second control signal are in a first logic state and a second logic state, respectively, to activate the switch device when the integrated circuit is in a normal operation mode,
wherein the first control signal and the second control signal are in the second logic state and the first logic state, respectively, to deactivate the switch device when the integrated circuit is in an electrostatic discharge (ESD) mode and an ESD event occurs on the I/O pad.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein the detection circuit comprises:
a first transistor, having a gate terminal coupled to a first node, a first terminal coupled to the second voltage supply node, and a second terminal coupled to a second node;
a first capacitor, coupled between the second voltage supply node and the first node;
a second transistor, having a gate terminal coupled to the second node, a first terminal coupled to the first node, and a second terminal coupled to the reference voltage supply node; and
a second capacitor, coupled between the second node and the reference voltage supply node.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the first control signal and the second control signal are generated at the first node and the second node.

### Claim 18 (depends on 16)

The integrated circuit of claim 16, wherein the detection circuit further comprises:
a first inverter chain, coupled to the first node, and comprising a first number of inverters connected in series; and
a second inverter chain, coupled to the second node, and comprising the first number of inverters connected in series,
wherein the first control signal and the second control signal are generated at a first point within the first inverter chain and a second point within the second inverter chain, respectively, and the first point and the second point have an equal number of inverters.

### Claim 19

A method, comprising:
determining an operation mode of an integrated circuit;
in response to the integrated circuit in an electrostatic discharge (ESD) mode, generating a first control signal in a first logic state and a second control signal in a second logic state to isolate a first terminal of a transmission gate from a second terminal of the transmission gate, wherein the first terminal and the second terminal are coupled to a pre-driver and a post-driver of the integrated circuit, respectively; and
suppressing a voltage difference across a victim transistor of the post-driver in response to an ESD event occurring on an input/output pad of the integrated circuit.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
in response to the integrated circuit in a normal operation mode, generating the first control signal in the second logic state and the second control signal in the first logic state to activate the transmission gate; and
transmitting a signal generated by the pre-driver of an internal circuit of the integrated circuit to the post-driver through the transmission gate.