# US 2026/0065950 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0065950 A1 - Document ID: US20260065950A1 - Status: Published application - Kind: A1 - Application number: 19/061,601 - Filed: 2025-02-24 - Published: 2026-03-05 - Earliest claimed: 2024-09-04 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hideto TAKEKIDA - Web page: https://patentgrep.com/patent/US20260065950A1 ## CPC - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/40: characterised by the peripheral circuit region - H10D 64/666: {the conductor further comprising additional layers} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract According to one embodiment, a semiconductor memory device includes: a substrate; a layer stack disposed above the substrate in a first direction; a first conductive layer disposed between the substrate and the layer stack; a memory pillar including a semiconductor film, extending in the first direction, and penetrating the first conductive layer; and a first member disposed apart from the memory pillar in a second direction intersecting the first direction, extending in the first direction, and penetrating the first conductive layer. The layer stack has a structure in which a first semiconductor layer, a second semiconductor layer, a second conductive layer, and a third conductive layer are stacked in order from a side of the substrate. The first semiconductor layer covers an end portion of the semiconductor film in the first direction and an end portion of the first member in the first direction. ## Claims ### Claim 1 A semiconductor memory device comprising: a substrate; a layer stack disposed above the substrate in a first direction; a first conductive layer disposed between the substrate and the layer stack; a memory pillar that includes a semiconductor film, extends in the first direction, and penetrates the first conductive layer; and a first member that is disposed apart from the memory pillar in a second direction intersecting the first direction, extends in the first direction, and penetrates the first conductive layer, wherein the layer stack has a structure in which a first semiconductor layer, a second semiconductor layer, a second conductive layer, and a third conductive layer are stacked in order from a side of the substrate, and the first semiconductor layer covers an end portion of the semiconductor film in the first direction and an end portion of the first member in the first direction. ### Claim 2 (depends on 1) The device according to claim 1, wherein a grain boundary of the first semiconductor layer and a grain boundary of the second semiconductor layer are discontinuous. ### Claim 3 (depends on 2) The device according to claim 2, wherein a grain diameter of the first semiconductor layer is different from a grain diameter of the second semiconductor layer. ### Claim 4 (depends on 3) The device according to claim 3, wherein the grain diameter of the first semiconductor layer is smaller than the grain diameter of the second semiconductor layer. ### Claim 5 (depends on 2) The device according to claim 2, wherein the layer stack has a structure in which an insulating layer is further provided between the first semiconductor layer and the second semiconductor layer. ### Claim 6 (depends on 5) The device according to claim 5, wherein the insulating layer is an oxide film or a nitride film. ### Claim 7 (depends on 1) The device according to claim 1, further comprising: a fourth conductive layer that is disposed between the first conductive layer and the layer stack, is spaced apart from the first conductive layer in the first direction, and is in contact with the first semiconductor layer, wherein the first member includes a conductor, and a first insulator that covers a side surface of the conductor in the second direction and an end surface of the conductor in the first direction, an end surface of the first insulator in the first direction has an inclined portion on a side not in contact with the conductor, and the inclined portion is in contact with the first semiconductor layer, and is in contact with the fourth conductive layer at a position below an upper surface of the fourth conductive layer in the first direction. ### Claim 8 (depends on 7) The device according to claim 7, wherein the first insulator includes a second insulator that covers the side surface of the conductor in the second direction and the end surface of the conductor in the first direction, and a third insulator that covers a side surface of the second insulator in the second direction. ### Claim 9 (depends on 1) The device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer include polysilicon. ### Claim 10 (depends on 1) The device according to claim 1, further comprising: a first chip including the substrate; and a second chip including the layer stack, the first conductive layer, the memory pillar, and the first member, wherein the second chip is bonded to the first chip. ### Claim 11 (depends on 1) The device according to claim 1, wherein the semiconductor memory device is a NAND flash memory. ### Claim 12 A semiconductor memory device comprising: a substrate; a layer stack disposed above the substrate in a first direction; a first conductive layer disposed between the substrate and the layer stack; a memory pillar that includes a semiconductor film, extends in the first direction, and penetrates the first conductive layer; and a first member that is disposed apart from the memory pillar in a second direction intersecting the first direction, extends in the first direction, and penetrates the first conductive layer, wherein the layer stack has a structure in which a first semiconductor layer, a second conductive layer, and a third conductive layer are stacked in order from a side of the substrate, the first member includes a conductor and a first insulator that covers a side surface of the conductor in the second direction, and the first semiconductor layer covers an end portion of the semiconductor film in the first direction and an end portion of the conductor in the first direction. ### Claim 13 (depends on 12) The device according to claim 12, further comprising: a fourth conductive layer that is disposed between the first conductive layer and the layer stack, is spaced apart from the first conductive layer in the first direction, and is in contact with the first semiconductor layer, wherein an end surface of the first insulator in the first direction is located below an upper surface of the conductor in the first direction and an upper surface of the fourth conductive layer in the first direction, and a side surface of the end portion of the conductor in the first direction and the end surface of the first insulator in the first direction are in contact with the first semiconductor layer. ### Claim 14 (depends on 13) The device according to claim 13, wherein the layer stack has a structure in which a second semiconductor layer is further provided between the first semiconductor layer and the second conductive layer. ### Claim 15 (depends on 14) The device according to claim 14, wherein the layer stack has a structure in which an insulating layer is further provided between the first semiconductor layer and the second semiconductor layer. ### Claim 16 (depends on 12) The device according to claim 12, wherein the first semiconductor layer includes polysilicon. ### Claim 17 A semiconductor memory device comprising: a substrate; a layer stack disposed above the substrate in a first direction; a first conductive layer disposed between the substrate and the layer stack; a memory pillar that includes a semiconductor film, extends in the first direction, and penetrates the first conductive layer; and a first member that is disposed apart from the memory pillar in a second direction intersecting the first direction, extends in the first direction, and penetrates the first conductive layer, wherein the layer stack has a structure in which a second conductive layer and a third conductive layer are stacked in order from a side of the substrate, and the second conductive layer covers an end portion of the semiconductor film in the first direction and an end portion of the first member in the first direction. ### Claim 18 (depends on 17) The device according to claim 17, further comprising: a fourth conductive layer that is disposed between the first conductive layer and the layer stack, is spaced apart from the first conductive layer in the first direction, and is in contact with the second conductive layer; wherein the first member includes a conductor, and a first insulator that covers a side surface of the conductor in the second direction and an end surface of the conductor in the first direction, an end surface of the first insulator in the first direction has an inclined portion on a side not in contact with the conductor, and the inclined portion is in contact with the second conductive layer, and is in contact with the fourth conductive layer at a position below an upper surface of the fourth conductive layer in the first direction. ### Claim 19 (depends on 18) The device according to claim 18, wherein the first insulator includes a second insulator that covers the side surface of the conductor in the second direction and the end surface of the conductor in the first direction, and a third insulator that covers a side surface of the second insulator in the second direction. ### Claim 20 (depends on 17) The device according to claim 17, wherein the second conductive layer includes titanium or titanium nitride, and the third conductive layer includes tungsten.