# US 2026/0064601 A1 · Application programming interface to allocate memory for shared virtual memory

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- Number: US 2026/0064601 A1
- Document ID: US20260064601A1
- Status: Published application
- Kind: A1
- Application number: 19/383,411
- Filed: 2025-11-07
- Published: 2026-03-05
- Earliest claimed: 2022-04-04
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corporation
- Inventors: James Christopher Beyer; Paul J. Sidenblad; Vyas Venkataraman; Chetan Gokhale; Cory Perry; Ying Liang; Harold Carter Edwards
- Web page: https://patentgrep.com/patent/US20260064601A1

## CPC

- G06F 12/1009: using page tables, e.g. page table structures
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 12/084: with a shared cache
- G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence)
- G06F 2009/45583: {Memory management, e.g. access or allocation}
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Apparatuses, systems, and techniques to facilitate memory management. In at least one embodiment, an application programming interface is performed to cause physical memory corresponding to shared virtual memory to be designated for use by a plurality of processors.

## Claims

### Claim 1

(canceled)

### Claim 2

One or more processors, comprising:
circuitry to, in response to a call of one or more application programming interfaces (APIs):
generate a memory handle to identify memory to be shared among one or more processors; and
cause the one or more processors to share the memory identified by the memory handle.

### Claim 3 (depends on 2)

The one or more processors of claim 2, wherein the circuitry is further to map physical memory locations to virtual memory addresses of the memory.

### Claim 4 (depends on 2)

The one or more processors of claim 2, wherein the one or more processors are located on different nodes of a compute cluster.

### Claim 5 (depends on 2)

The one or more processors of claim 2, wherein the circuitry is further to coordinate sharing of the memory by the one or more processors, the memory being virtual memory.

### Claim 6 (depends on 2)

The one or more processors of claim 2, wherein the memory comprises virtual memory and the memory handle comprises a virtual memory handle.

### Claim 7 (depends on 2)

The one or more processors of claim 2, wherein the circuitry is further to disable access to the memory by the one or more processors.

### Claim 8 (depends on 2)

The one or more processors of claim 2, wherein the circuitry is further to provide the memory handle to at least two of the one or more processors, and each processor is to use the memory handle to map respective physical memory locations to the memory.

### Claim 9

A system, comprising:
one or more processors to, in response to a call of one or more application programming interfaces (APIs):
generate a memory handle to identify memory to be shared among one or more processors; and
cause the one or more processors to share the memory identified by the memory handle.

### Claim 10 (depends on 9)

The system of claim 9, wherein the memory comprises virtual memory and the memory handle comprises a virtual memory handle.

### Claim 11 (depends on 9)

The system of claim 9, wherein the one or more processors are further to map physical memory locations to virtual memory addresses of the memory.

### Claim 12 (depends on 9)

The system of claim 9, wherein the one or more processors are further to allocate physical memory to the one or more processors based on one or more requirements for the memory.

### Claim 13 (depends on 9)

The system of claim 9, wherein the memory handle comprises a multicast memory handle that is to communicate with the one or more processors.

### Claim 14 (depends on 9)

The system of claim 9, wherein the one or more processors are further to synchronize sharing of the memory by the one or more processors, the memory being virtual memory.

### Claim 15 (depends on 8)

The system of claim 8, wherein the one or more processors are further to allocate physical memory corresponding to the memory.

### Claim 16

A method, comprising:
in response to a call of one or more application programming interfaces (APIs), generating a memory handle to identify memory to be shared among one or more processors; and
causing the one or more processors to share the memory identified by the memory handle.

### Claim 17 (depends on 16)

The method of claim 16, wherein the memory handle comprises a multicast memory handle that is to communicate with the one or more processors.

### Claim 18 (depends on 16)

The method of claim 16, further comprising allocating physical memory for the one or more processors corresponding to the memory comprising virtual memory.

### Claim 19 (depends on 16)

The method of claim 16, further comprising synchronizing sharing of the memory by the one or more processors.

### Claim 20 (depends on 16)

The method of claim 16, wherein the memory comprises virtual memory and the memory handle is a virtual memory handle.

### Claim 21 (depends on 16)

The method of claim 16, further comprising communicating with the one or more processors using the memory handle, which comprises a multicast memory handle.