Memory, memory module, and semiconductor system
AssigneeSK hynix Inc.
InventorsMin Su PARK, Kyung Whan KIM, Choung Ki SONG
Life of this patent
Estimating the term…
Abstract
A semiconductor system may include a command address bus, a data bus, a management bus, a memory module including multiple memories and coupled to the command address bus, data bus and management bus, a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation and a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories.
Claims36
A semiconductor system comprising:
- a command address bus;
- a data bus;
- a management bus;
- a memory module including multiple memories and coupled to the command address bus, data bus and management bus;
- a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation;
- and
- a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories.
An operating method of a semiconductor system including a controller and multiple memories coupled to the controller through in-band interface and a baseboard management controller coupled to the multiple memories through side-band interfaces, the operating method comprising:
- controlling, by the controller, the multiple memories through the in-band interface;
- selecting, by the baseboard management controller, one of the multiple memories through the side band interface;
- receiving, by the baseboard management controller, information from a register of the selected memory;
- and
- requesting, by the baseboard management controller to the selected memory, a processing operation for fail information when the information includes the fail information.
A memory comprising:
- a memory cell array configured to perform a read operation or a write operation based on a clock, a command, and an address that are provided through a command/address bus and data that is provided through a data bus;
- an error correction circuit configured to correct an error of data output as a result of the read operation of reading the data from a memory area within the memory cell array and to store therein a fail address indicating the memory area at which the error has occurred;
- and
- an alert address processing circuit configured to store therein, when the provided address is identical with the fail address, information provided from the error correction circuit, for determining an error rate of the data.
An operating method of a semiconductor system, the operating method comprising:
- performing, through an in-band interface, a read operation of reading data from a memory area;
- transmitting, through a side-band interface, information of a fail address indicating the memory area, at which an ECC error has occurred in the data;
- determining an error rate based on the information;
- and
- registering the fail address as an alert address when the error rate is greater than a preset error rate.
A memory comprising:
- a temperature sensor configured to sense a temperature of the memory;
- a temperature register configured to store therein alert temperature information;
- and
- an alert temperature information generation circuit configured to store the alert temperature information in the temperature register when the temperature is greater than a preset range.
Dependencies are inferred from the claim text.