Port selection for hardware queuing management device

A processor comprising:

• a plurality of processing engines;
• and
• a plurality of hardware queue manager (HQM) devices, each HQM device to queue data requests for a different subset of the plurality of processing engines,
• wherein at least one processing engine is to execute a first set of instructions to:
• detect a first enqueue instruction to enqueue data in a first HQM device of the plurality of HQM devices;
• in response to a detection of the first enqueue instruction, perform a look-up of the first HQM device in a data structure to determine a recommended port for the first HQM device;
• and
• transmit the first enqueue instruction using the recommended port for the first HQM device.

A machine-readable medium storing instructions that upon execution cause a processor to:

• identify a plurality of hardware queue manager (HQM) devices to be profiled, each HQM device to queue data requests for a different subset of a plurality of processing engines;
• for each HQM device of the plurality of HQM devices:
• transmit at least one test message to each producer port of the HQM device;
• determine a performance metric for each producer port of the HQM device;
• order the producer ports according to an order of the performance metrics;
• and
• create a set of entries in a stored data structure to identify the producer ports of the HQM device in the order of the performance metrics.

A system comprising:

• a processor comprising a plurality of processing engines and a plurality of hardware queue manager (HQM) devices, wherein at least one processing engine is to execute instructions to:
• detect a first enqueue instruction to enqueue data in a first HQM device of the plurality of HQM devices;
• in response to a detection of the first enqueue instruction, perform a look-up of the first HQM device in a stored data structure to determine a recommended port for the first HQM device;
• and
• transmit the first enqueue instruction using the recommended port for the first HQM device;
• and
• a system memory coupled to the processor.