# US 2026/0064418 A1 · Instruction control method, data caching method, and related products

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- Number: US 2026/0064418 A1
- Document ID: US20260064418A1
- Status: Published application
- Kind: A1
- Application number: 19/106,599
- Filed: 2023-08-02
- Published: 2026-03-05
- Earliest claimed: 2022-09-02
- Assignees: Shanghai Cambricon Information Technology Co., Ltd.
- Applicants: Shanghai Cambricon Information Technology Co., Ltd
- Inventors: Bingrui WANG; Dong HAN; Yongzheng HAO
- Web page: https://patentgrep.com/patent/US20260064418A1

## CPC

- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 9/3824: {Operand accessing}
- G06F 9/3834: {Maintaining memory consistency}
- G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding}
- G06F 9/384: {Register renaming}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 12/0842: for multiprocessing or multitasking
- G06F 12/0857: {by multiple requestors}
- G06F 12/0862: with prefetch
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0866: for peripheral storage systems, e.g. disk cache
- G06F 2212/1024: Latency reduction
- G06F 2212/452: Instruction code
- G06F 2212/502: using adaptive policy
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

This disclosure discloses an instruction control method, instruction control apparatus, processor, chip, and board card. The processor can be included as a computing apparatus in a combination processing apparatus, which may also include interface devices and other processing apparatus. The computing apparatus interacts with other processing apparatuses to jointly complete computing operations specified by the user. The combined processing apparatus may also include a storage apparatus, which is connected to the computing apparatus and other processing apparatuses respectively, for storing data of the computing apparatus and other processing apparatuses. The disclosed solution provides an instruction control method that can enhance instruction level parallelism and improve processing efficiency.

## Claims

### Claim 1

An instruction control apparatus, comprising:
an instruction decoder configured to decode a memory access instruction, wherein the memory access instruction is configured to read data from a source end storage circuit and write the data into a destination end storage circuit;
an instruction cache unit configured to cache the decoded memory access instruction; and
an instruction transmission controller configured to transmit in advance the memory access instruction in the instruction cache unit to read the data from the source end storage circuit and cache the data to a data cache in response to existence of only dependency on the destination end storage circuit between the memory access instruction and a preceding instruction, and send a blocking signal which blocks the data read by the memory access instruction to the data cache.

### Claim 2 (depends on 1)

The instruction control apparatus of claim 1, further comprising:
a dependency recording unit configured to record dependency relationship of a storage resource of a memory access instruction; and
the instruction transmission controller further configured to send a release signal for releasing the data read by the memory access instruction to the data cache when it is determined that the dependency on the destination end storage circuit has been released based on the dependency relationship record of the dependency recording unit.

### Claim 3 (depends on 2)

The instruction control apparatus of claim 2, wherein the instruction transmission controller is further configured to determine whether only dependency on a destination end storage circuit exists between the memory access instruction and the preceding instruction based on the dependency relationship record of the dependency recording unit.

### Claim 4 (depends on 3)

The instruction control apparatus of claim 3, wherein the dependency recording unit is further configured to update the dependency relationship of the source end storage circuit in response to receiving a dependency release signal for the source end storage circuit, wherein the dependency release signal is a synchronization release signal for the source end storage circuit, and the synchronization release signal is based on storage range accessible by an instruction stream of each consumption end in the synchronization instruction, and is released separately for a production end according to the storage range.

### Claim 5 (depends on 1)

The instruction control apparatus of claim 1, wherein the instruction decoder is further configured to:
suspend decoding of subsequent instructions in response to receiving a signal indicating that the data cache space is insufficient.

### Claim 6 (depends on 1)

The instruction control apparatus of claim 1, wherein the preceding instruction and the memory access instruction are in the same instruction queue or in different instruction queue.

### Claim 7 (depends on 1)

The instruction control apparatus of claim 1, wherein the data cache is a reordering cache.

### Claim 8

A data cache configured to:
cache data read by a memory access instruction; and
in response to receiving a blocking signal to block the data read by the memory access instruction, block the data read by the memory access instruction in the data cache.

### Claim 9 (depends on 8)

The data cache of claim 8, further configured to:
in response to receiving a release signal to release the data read by the memory access instruction, return the data to the destination end storage circuit of the memory access instruction.

### Claim 10 (depends on 8)

The data cache of claim 8 , further configured to:
in response to the amount of data blocked in the data cache exceeding a predetermined threshold, send a signal indicating that the data cache space is insufficient to an instruction decoder to suspend decoding of subsequent instructions.

### Claim 11 (depends on 8)

The data cache of claim 8, wherein the data cache is a reordering cache.

### Claim at position 12

12-14. (canceled)

### Claim 15

A memory access instruction control method, comprising:
decoding a memory access instruction, wherein the memory access instruction is configured to read data from a source end storage circuit and write the data into a destination end storage circuit;
in response to existence of only dependency on the destination end storage circuit between the memory access instruction and a preceding instruction, transmitting in advance the memory access instruction to read the data from the source end storage circuit and cache the data to a data cache; and
sending a blocking signal which blocks the data read by the memory access instruction to the data cache.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
in response to completion of memory access to the destination end storage circuit by the preceding instruction, releasing the dependency on the destination end storage circuit; and
sending a release signal for releasing the data read by the memory access instruction to the data cache.

### Claim 17 (depends on 15)

The method of claim 15, wherein in response to existence of only the dependency on the destination end storage circuit between the memory access instruction and the preceding instruction comprising:
receiving a dependency release signal for the source end storage circuit.

### Claim 18 (depends on 17)

The method of claim 17, wherein the dependency release signal for the source end storage circuit is a synchronization release signal for the source end storage circuit, and the synchronization release signal is based on storage range accessible by an instruction stream of each consumption end in the synchronization instruction, and is released separately for a production end according to the storage range.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
suspending decoding of subsequent instructions in response to receiving a signal indicating that the data cache space is insufficient.

### Claim 20 (depends on 15)

The method of claim 15, wherein the preceding instruction and the memory access instruction are in the same instruction queue or in different instruction queue.

### Claim 21 (depends on 15)

The method of claim 15, wherein the data cache is a reordering cache.

### Claim at position 20

22-24. (canceled)