Device and Method of Operation Thereof

A device comprising:

• a semiconductor chip including:
• an input clock signal generator configured to generate a first input clock signal;
• a distribution network configured to generate a plurality of second input clock signals, each corresponding to the first input clock signal, and a plurality of first output clock signals, each corresponding to the second input clock signal;
• an output clock signal generator configured to generate a plurality of second output clock signals, each corresponding to the first output clock signal;
• a first clock signal grid interconnecting inputs or outputs of the distribution network and configured to facilitate the substantially simultaneous arrival of the first output clock signals at the output clock signal generator;
• and
• a conductive layer formed over a surface of the semiconductor chip and connected to the first clock signal grid.

A method for synchronizing a first semiconductor chip and a second semiconductor chip, the method comprising:

• the first semiconductor chip generating a first input clock signal;
• the first semiconductor chip distributing a plurality of second input clock signals, each corresponding to the first input clock signal;
• the first semiconductor chip synchronizing the second input clock signals;
• and
• the second semiconductor chip, bonded to the first semiconductor chip, receiving and synchronizing the second input clock signals.