Apparatus and methods for jitter testing of clock signals

Abstract

Apparatus and methods for jitter testing of clock signals are disclosed. In certain embodiments, a jitter measuring circuit is used to obtain jitter measurements of a PLL's clock signal in an analog domain. For example, the analog jitter measurements can be generated by discharging a capacitor to a voltage that is proportional to a phase difference between a test clock signal from the PLL and a reference clock signal that can be assumed to be ideal. Additionally, the analog jitter measurements are digitized and processed (for instance, using digital signal processing) to generate an estimate of jitter.

Dependencies are inferred from the claim text.