# US 2026/0063705 A1 · Fully integrated process monitor and threshold voltage extractor circuit

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- Number: US 2026/0063705 A1
- Document ID: US20260063705A1
- Status: Published application
- Kind: A1
- Application number: 19/315,576
- Filed: 2025-08-31
- Published: 2026-03-05
- Earliest claimed: 2024-09-05
- Assignees: Bar-Ilan University
- Applicants: Bar-Ilan University
- Inventors: Joseph Shor; Ido Shpernat; Asaf Feldman
- Web page: https://patentgrep.com/patent/US20260063705A1

## CPC

- G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]}
- G01R 31/2621: {for testing field effect transistors, i.e. FET's}
- G01R 31/2879: {related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- H03M 3/43: {the quantiser being a single bit one}
- H03M 3/464: {Details of the digital/analogue conversion in the feedback path}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A new architecture of an on-die process monitor circuit is described, without limitation, in 28 nm. The circuit can extract the threshold voltage, VTH, and random mismatch of a transistor using multiple extraction methods, such as but not limited to, the second derivative method. A sigma-delta modulator analog-to-digital converter may sample the output to enable on-die processing of the results. A VDS voltage control loop may be used to enable VTH extraction in both the linear and saturation regions of the device. The circuit may have a compact area of 5510 μm2.

## Claims

### Claim 1

A process monitor for a transistor device comprising:
a current source circuitry configured to provide an input current (IIN) to a drain of at least one Device Under Test (DUT), which comprises an NMOS (n-type metal oxide semiconductor) or a PMOS (n-type metal oxide semiconductor);
a drain-source voltage regulation circuitry configured to regulate a drain-source voltage (referred to as VDS for NMOS, VSD for PMOS) of said at least one DUT;
a gate-source voltage regulation circuitry configured to regulate a gate-source voltage (VGS) of said at least one DUT versus said input current so that said drain-source voltage remains constant and said at least one DUT is in a linear region or in a saturation region or between the linear and saturation regions; and
a measurement circuitry configured to measure said gate-source voltage to derive therefrom an operational parameter of said transistor device.

### Claim 2 (depends on 1)

The process monitor according to claim 1, wherein said operational parameter is a threshold voltage of said at least one DUT.

### Claim 3 (depends on 1)

The process monitor according to claim 1, wherein said operational parameter is a threshold voltage of said at least one DUT in said linear region.

### Claim 4 (depends on 1)

The process monitor according to claim 1, wherein said operational parameter is a threshold voltage of said at least one DUT in said saturation region.

### Claim 5 (depends on 1)

The process monitor according to claim 1, wherein said operational parameter is a mobility of a silicon substrate of said at least one DUT.

### Claim 6 (depends on 1)

The process monitor according to claim 1, wherein said operational parameter is a random variation of said at least one DUT.

### Claim 7 (depends on 1)

The process monitor according to claim 1, wherein said current source circuitry comprises a switched capacitor circuit.

### Claim 8 (depends on 7)

The process monitor according to claim 7, wherein said switched capacitor circuit comprises a reference voltage which is applied to at least one switching capacitor to generate said input current which equals C*V*F, where C is capacitance of said at least one switching capacitor, V is said reference voltage and F is a switching frequency, and said input current is mirrored to said at least one DUT.

### Claim 9 (depends on 8)

The process monitor according to claim 8, wherein said current source circuitry is configured to vary said input current by changing a clock frequency and a core capacitance in said switched capacitor circuit.

### Claim 10 (depends on 1)

The process monitor according to claim 1, wherein said at least one DUT comprises more than one DUT, and further comprising a multiplexer configured to select which DUT is to be measured from said more than one DUT.

### Claim 11 (depends on 1)

The process monitor according to claim 1, wherein said gate-source voltage is forwarded to a discrete-time sigma-delta modulator (DT-SDM) analog-to-digital converter.