# US 2026/0061202 A1 · Hybrid Magnetic-Ultrasonic Wireless Interrogation of Millimeter-Scale Biomedical Implants With Magnetoelectric Transducer

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- Number: US 2026/0061202 A1
- Document ID: US20260061202A1
- Status: Published application
- Kind: A1
- Application number: 19/385,766
- Filed: 2025-11-11
- Published: 2026-03-05
- Earliest claimed: 2023-12-13
- Assignees: The Penn State Research Foundation
- Applicants: The Penn State Research Foundation
- Inventors: Sumanta Kumar Karan; Sujay Hosur; Bed Poudel; Mehdi Kiani; Shashank Priya; Zeinab Kashani
- Web page: https://patentgrep.com/patent/US20260061202A1

## CPC

- A61N 1/37223: {Circuits for electromagnetic coupling}
- A61N 1/3787: {from an external energy source}
- H02J 50/10: using inductive coupling
- H03K 17/6872: {using complementary field-effect transistors}
- A61N: ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY (measurement of bioelectric currents A61B; surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body A61B18/00; anaesthetic apparatus in general A61M; incandescent lamps H01K; infrared radiators for heating H05B)
- H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Embodiments can relate to an implant stimulation and recording system. The system can include a receiver. The system can include an interrogator having a transmitter coil and an ultrasound transducer. The system can include an implant having an integrated circuit and a magnetoelectric transducer. Low-frequency magnetic fields are generated by the transmitter coil and are converted into an electric voltage by the magnetoelectric transducer. Ultrasound energy is generated by the transducer and converted into an electric voltage by the magnetoelectric transducer. When voltage is applied to the magnetoelectric transducer, the magnetoelectric transducer generates magnetic fields and ultrasound waves, wherein the receiver detects the magnetic fields and ultrasound waves generated by the magnetoelectric transducer.

## Claims

### Claim 1

An implant stimulation and recording system, comprising:
a receiver;
an interrogator comprising a transmitter coil and an ultrasound transducer;
an implant comprising an integrated circuit and a magnetoelectric transducer;
wherein low-frequency magnetic fields are generated by the transmitter coil and converted into an electric voltage by the magnetoelectric transducer;
wherein ultrasound energy is generated by the transducer and converted into an electric voltage by the magnetoelectric transducer; and
wherein, when voltage is applied to the magnetoelectric transducer, the magnetoelectric transducer generates magnetic fields and ultrasound waves, wherein the receiver detects the magnetic fields and ultrasound waves generated by the magnetoelectric transducer.

### Claim 2 (depends on 1)

The implant stimulation and recording system of claim 1, wherein:
the implant includes a storage capacitor.

### Claim 3 (depends on 1)

The implant stimulation and recording system of claim 1, wherein:
the integrated circuit includes: an integrated power management and data transmitter (IPMDT); a biphasic alternating current stimulator, an active charge balancer circuit, a recording low-noise amplifier, an analog-to-time converter configured for uplink communication using magnetic fields and ultrasound waves, and a calibration unit.

### Claim 4 (depends on 3)

The implant stimulation and recording system of claim 3, wherein:
the IPMDT is connected to a first voltage output (VME1) of the magnetoelectric transducer and a voltage output (VME2) of the magnetoelectric transducer; and
the IPMDT includes a bridge circuit comprising a first branch (B1) with a first switch (S1), a second branch (B2) with a second switch (S2), a third branch (B3) with a third switch (S3), a fourth branch (B4) with a fourth switch (S4), and a storage capacitor (Cext).

### Claim 5 (depends on 4)

The implant stimulation and recording system of claim 4, wherein:
B1 is connected to node N1 and node N2, B2 is connected to node N1 and node N4, B3 is connected to node N3 and node N4, and B4 is connected to node N2 and node N3;
N1 is connected to a positive power supply (VDD) and to Cext;
N3 is connected to ground (GND) and to (Cext);
S1 is a P-channel Metal-Oxide-Semiconductor (PMOS) transistor having a source connected to VME1, a gate, and a drain connected to VDD;
S2 is a PMOS transistor having a source connected to VME2, a gate, and a drain connected to VDD;
S3 is a N-channel Metal-Oxide-Semiconductor (NMOS) transistor having a source connected to VME2, a gate, and a drain connected to GND;
S4 includes a first NMOS transistor and a second NMOS transistor, wherein:
the first NMOS transistor has a source connected to VME1, a gate, and a drain connected to a source of the second NMOS transistor;
the second NMOS transistor has a source connected to the drain of the first NMOS transistor, a gate, and a drain connected to GND.

### Claim 6 (depends on 3)

The implant stimulation and recording system of claim 3, wherein:
the biphasic alternating current stimulator includes a charge pump circuit, a level shifter circuit, and a high-voltage tolerant switch circuit.

### Claim 7 (depends on 6)

The implant stimulation and recording system of claim 6, wherein:
the charge pump circuit comprises:
a first N-channel Metal-Oxide-Semiconductor (NMOS) transistor, a second P-channel Metal-Oxide-Semiconductor (PMOS) transistor, a third PMOS transistor, and a fourth NMOS transistor;
the first NMOS transistor includes a source connected to node N3, a gate connected to node N2, a drain connected to node N1;
the second PMOS transistor includes a source connected to node N4, a gate connected to node N2, a drain connected to node N3;
N3 is connected to a pumping capacitor Cp1 whose other end is connected to a first clock (CLK1);
the third PMOS transistor includes a source connected to node N4, a gate connected to node N3, a drain connected to node N2;
a second pumping capacity Cp2 is connected between a second clock (CLK2) and to N2; and
the fourth PMOS transistor includes a source connected to N2, a gate connected to N3, and a drain connected to N1.

### Claim 8 (depends on 6)

The implant stimulation and recording system of claim 6, wherein:
the level shifter circuit, comprises:
a first P-channel Metal-Oxide-Semiconductor (PMOS) transistor, a second PMOS transistor, a third N-channel Metal-Oxide Semiconductor (NMOS) transistor, and a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and an eight PMOS transistor;
the first PMOS transistor includes a source connected to node N1, a gate connected to node N2, and a drain connected to node N3;
the second PMOS transistor includes a source connected to N3, a gate connected to node N4, and a drain connected to node N5;
the third NMOS transistor includes a drain connected to N5, a gate connected to N4, and a source connected to N6;
the fourth NMOS transistor includes a source drain to N6, a gate connected to node N7, and a source connected to node N8;
N7 is connected to a control signal (Vin), and N8 is connected to ground (GND);
the fifth NMOS transistor includes a drain connected to node N9, a gate connected to node N10, and a source connected to node N8;
N7 is connected to a first inverter (INV1);
the sixth NMOS transistor includes a drain connected to node N11, a gate connected to node N12, and a source connected to N9;
the seventh PMOS transistor includes a source connected to node N13, a gate connected to node N12, and a drain connected to N11; and
the eighth PMOS transistor includes a source connected to N1, a gate connected N2 and to a second inverter (INV2), and a drain connected to N13.

### Claim 9 (depends on 6)

The implant stimulation and recording system of claim 6, wherein:
the high-voltage tolerant switch circuit comprises:
a first P-channel Metal-Oxide-Semiconductor (PMOS) transistor, a second PMOS transistor, a third N-channel Metal-Oxide-Semiconductor (NMOS) transistor, and a fourth NMOS transistor;
the first PMOS transistor includes a source connected to node N1, a gate connected to node N2, and a drain connected to node N3;
N2 is connected to a voltage control signal (VMP1);
the second PMOS transistor includes a source connected to N3, a gate connected to node N4, and a drain connected to node N5;
N4 is connected to voltage control signal (VMP2);
the third NMOS transistor includes a source connected to N7, a gate connected to node N6, and a drain connected to node N1;
N6 is connected to voltage control signal (VMN1);
the fourth NMOS transistor includes a source connected to N5, a gate connected to node N8, and a drain connected to N7; and
N8 is connected to voltage control signal (VMN2).

### Claim 10 (depends on 3)

The implant stimulation and recording system of claim 3, wherein:
the biphasic alternating current stimulator circuit comprises:
a first high voltage switch connected to node N1 and node N2;
a second high voltage switch connected to N1 and node N3;
N1 is connected to a voltage source (VME1);
a first N-channel Metal-Oxide-Semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;
the first NMOS transistor includes a drain connected to N2, a gate, and a source connected to node N4;
the second NMOS transistor includes a drain connected to N4, a gate, and a source connected to node N5;
N5 is connected to a first ground (GND1);
the third NMOS transistor includes a drain connected to N3, a gate, and a source connected to node N6;
the fourth NMOS transistor includes a drain connected to N6, a gate, and a source connected to node N7;
N7 is connected to a second ground (GND2).

### Claim 11 (depends on 3)

The implant stimulation and recording system of claim 3, wherein:
the recording low-noise amplifier comprises:
a first op-amp (OP-AMP1), a second op-amp (OP-AMP2), a first circuit block, a second circuit block, a third circuit block, and a fourth circuit block;
OPAMP1 includes a first input connected to node N2, a second input connected to node N3, a first output connected to node N4, and a second output connected to node N5;
N2 is connected to a first capacitor (C1), and C1 is connected to node N1, wherein N1 is connected to a input voltage signal (Vin−);
N3 is connected to a second capacitor (C2), and C2 is connected to node N8, wherein N8 is connected to a input voltage signal (Vin+);
N4 is connected to a third capacitor (C3), and C3 is connected to node N6;
N5 is connected to a fourth capacitor (C4), and C4 is connected to node N7;
OP-AMP2 includes a first input connected to N6, a second input connected to N7, and an output connected to node N9;
the first circuit block comprises:
a fifth capacitor (C5) connected to node N2 and node N4;
a first P-channel Metal-Oxide-Semiconductor (PMOS) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor;
the first PMOS transistor includes a drain connected to node N2, a gate connected to node N13, and a source connected to N13;
the second PMOS transistor includes a drain connected to node N4, a gate connected to N13, and a source connected to N13;
each of the third, fourth, fifth, sixth, and seventh PMOS transistors includes a source, a gate, and a drain;
for the third PMOS transistor, the drain is connected to N12, the gate is connected to node N15, and the source connected to the drain of the fourth PMOS transistor;
for the fourth PMOS transistor, the drain is connected to the source of the third PMOS transistor, the gate is connected to node N15, and the source connected to the drain of the fifth PMOS transistor;
for the fifth PMOS transistor, the drain is connected to the source of the fourth PMOS transistor, the gate is connected to node N15, and the source connected to the drain of the sixth PMOS transistor;
for the sixth PMOS transistor, the drain is connected to the source of the fifth PMOS transistor, the gate is connected to node N15, and the source connected to the drain of the seventh PMOS transistor;
for the seventh PMOS transistor, the drain is connected to the source of the sixth PMOS transistor, the gate is connected to node N15, and the source connected to N4;
the second circuit block comprises:
a sixth capacitor (C6) connected to node N6 and node N17, wherein N17 is connected to N9;
a seventh capacitor (C7) connected to node N6 and node N17 via a first switch (D1), wherein N19 is connected to N17;
an eighth capacitor (C8) connected to node N6 and node N17 via a second switch (D2);
a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, and a fifteenth PMOS transistor;
the ninth PMOS transistor includes a drain connected to node N6, a gate connected to node N23, and a source connected to N23, wherein N6 is connected to N17;
the tenth PMOS transistor includes a drain connected to node N24, a gate connected to N23, and a source connected to N23, wherein N17 is connected to N6;
each of the eleventh, twelfth, thirteenth, fourteenth, and fifteenth PMOS transistors includes a source, a gate, and a drain;
for the eleventh PMOS transistor, the drain is connected to N22, the gate is connected to node N25, and the source connected to the drain of the twelfth PMOS transistor;
for the twelfth PMOS transistor, the drain is connected to the source of the eleventh PMOS transistor, the gate is connected to node N25, and the source connected to the drain of the thirteenth PMOS transistor;
for the thirteenth PMOS transistor, the drain is connected to the source of the twelfth PMOS transistor, the gate is connected to node N25, and the source connected to the drain of the fourteenth PMOS transistor;
for the fourteenth PMOS transistor, the drian is connected to the source of the thirteenth PMOS transistor, the gate is connected to node N25, and the source connected to the drain of the fifteenth PMOS transistor;
for the fifteenth PMOS transistor, the drain is connected to the source of the fourteenth PMOS transistor, the gate is connected to node N25, and the source connected to N17;
the third circuit block comprises:
a ninth capacitor (C9) connected to node N3 and node N5;
a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty first PMOS transistor, and a twenty second PMOS transistor;
the sixteenth PMOS transistor includes a drain connected to node N3, a gate connected to node N29, and a source connected to N29;
the seventeenth PMOS transistor includes a drain connected to node N5, a gate connected to N29, and a source connected to N29;
each of the eighteenth, nineteenth, twentieth, twenty first, and twenty second PMOS transistors includes a source, a gate, and a drain;
for the eighteenth PMOS transistor, the drain is connected to N28, the gate is connected to node N31, and the source connected to the drain of the nineteenth PMOS transistor;
for the nineteenth PMOS transistor, the drain is connected to the source of the eighteenth PMOS transistor, the gate is connected to node N31, and the source connected to the drain of the twentieth PMOS transistor;
for the twentieth PMOS transistor, the drain is connected to the source of the nineteenth PMOS transistor, the gate is connected to node N31, and the source connected to the drain of the twenty first PMOS transistor;
for the twenty first PMOS transistor, the drain is connected to the source of the twentieth PMOS transistor, the gate is connected to node N31, and the source connected to the drain of the twenty second PMOS transistor;
for the twenty second PMOS transistor, the drain is connected to the source of the twenty first PMOS transistor, the gate is connected to node N31, and the source connected to N5;
the fourth circuit block comprises:
a tenth capacitor (C10) connected to node N7 and node N33;
an eleventh capacitor (C11) connected to node N32 and node N33 via a third switch (D3;
a twelfth capacitor (C12) connected to node N7 and node N33 via a fourth switch (D4);
a twenty third PMOS transistor, a twenty fourth PMOS transistor, a twenty fifth PMOS transistor, a twenty sixth PMOS transistor, a twenty seventh PMOS transistor, a twenty eighth PMOS transistor, and a twenty ninth PMOS transistor;
the twenty third PMOS transistor includes a drain connected to node N33, a gate connected to node N39, and a drain connected to N39;
the twenty fourth PMOS transistor includes a drain connected to node N7, a gate connected to N39, and a drain connected to N39;
each of the twenty fifth, twenty sixth, twenty seventh, twenty eighth, and twenty ninth PMOS transistors includes a source, a gate, and a drain;
for the twenty fifth PMOS transistor, the drain is connected to node N41, the gate is connected to node N43, and the source connected to the drain of the twenty sixth PMOS transistor;
for the twenty sixth PMOS transistor, the drain is connected to the source of the twenty fifth PMOS transistor, the gate is connected to N43, and the source connected to the drain of the twenty seventh PMOS transistor;
for the twenty seventh PMOS transistor, the drain is connected to the source of the twenty sixth PMOS transistor, the gate is connected to N43, and the drain connected to the drain of the twenty eighth PMOS transistor;
for the twenty eighth PMOS transistor, the drain is connected to the source of the twenty seventh PMOS transistor, the gate is connected to N43, and the source connected to the drain of the twenty nineth PMOS transistor;
for the twenty nineth PMOS transistor, the drain is connected to the source of the twenty eighth PMOS transistor, the gate is connected to node N43, and the source connected to node N7.