Presettable ramp driver to drive adc for image sensor

A method of presetting a presettable ramp driver to prepare for an analog-to-digital converter (ADC) operation, comprising:

• setting a first switch control signal to a first switch voltage to turn a first switch on, and setting a second switch control signal to a second switch voltage to turn a second switch on;
• after a first time duration, flipping the second switch control signal to an inverted voltage of the second switch voltage to turn the second switch off;
• after a second time duration, flipping the first switch control signal to an inverted voltage of the first switch voltage to turn the first switch off;
• after a third time duration, generating an auto-zero (AZ) voltage pulse to turn an AZ switch of an ADC comparator on, and after a fourth time duration to turn the AZ switch of the ADC comparator off, to reset the ADC;
• and
• receiving a pixel signal from a bitline to couple to a first input of an ADC comparator, and receiving a ramp signal from a ramp generator to couple through the presettable ramp driver into a second input of the ADC comparator.

A method of presetting a presettable ramp driver to prepare for an analog-to-digital converter (ADC) operation, comprising:

• setting a bias voltage to a bias value that is between 0V and a supply voltage AVDD to bias a bias transistor for its optimal operation, setting a first switch control signal to a first switch voltage to turn a first switch on, and setting a second switch control signal to a second switch voltage to turn a second switch on;
• after a first time duration, flipping the first switch control signal to an inverted voltage of the first switch voltage to turn the first switch off;
• after a second time duration, flipping the second switch control signal to an inverted voltage of the second switch voltage, to turn the second switch off;
• after a third time duration, generating an auto-zero (AZ) voltage pulse to turn an AZ switch of an ADC comparator on, and after a fourth time duration to turn the AZ switch of the ADC comparator off, to reset the ADC;
• and
• receiving a pixel signal from a bitline to couple to a first input of an ADC comparator, and receiving a ramp signal from a ramp generator to couple through the presettable ramp driver into a second input of the ADC comparator.

A method of presetting a presettable ramp driver to prepare for an analog-to-digital converter (ADC) operation, comprising:

• setting a bias voltage to a bias value that is between 0V and a supply voltage AVDD to bias a bias transistor for its optimal operation, setting a first switch control signal to a first switch voltage to turn a first switch on, and setting a second switch control signal to a second switch voltage to turn a second switch on;
• after a first time duration, flipping the second switch control signal to an inverted voltage of the second switch voltage to turn the second switch off;
• after a second time duration, flipping the first switch control signal to an inverted voltage of the first switch voltage, to turn the first switch off;
• after a third time duration, generating an auto-zero (AZ) voltage pulse to turn an AZ switch of an ADC comparator on, and after a fourth time duration to turn the AZ switch of the ADC comparator off, to reset the ADC;
• and
• receiving a pixel signal from a bitline to couple to a first input of an ADC comparator, and receiving a ramp signal from a ramp generator to couple through the presettable ramp driver into a second input of the ADC comparator.

A readout analog-to-digital converter (ADC) image sensing system, comprising:

• a pixel array;
• a control circuitry coupled to the pixel array to control operation of the pixel array;
• a readout circuitry controlled by the control circuitry and coupled to the pixel array through a bitline to read out analog image data from the pixel array, wherein the readout circuitry comprises a readout ADC to convert analog image data to digital image data, wherein the readout ADC comprises:
• a plurality of bitlines;
• a plurality of ADCs;
• a plurality of ADC comparators, wherein each ADC comparator is associated with an ADC of the plurality of ADCs;
• a plurality of sample capacitors, wherein each sample capacitor is coupled between a bitline of the plurality of bitlines and a first input of an ADC comparator of the plurality of ADC comparators;
• a ramp generator;
• a plurality of presettable ramp drivers, wherein each presettable ramp driver is coupled between the ramp generator and at least two second inputs of ADC comparators;
• and
• a plurality of ramp counters, wherein each ramp counter is coupled to an output of the ADC comparator of the plurality of the ADCs to latch and provide digital image data of an ADC associated with the ADC comparator when the output of the ADC comparator flips its value;
• and
• a function logic coupled to the readout circuitry to receive digital image data.