Clock generator and device including the same

A clock generator comprising:

• a Digital-to-Time Converter (DTC) configured to receive a first reference clock signal from outside the clock generator, and output a second reference clock signal by adjusting, a phase of the first reference clock signal received from outside the clock generator, based on a DTC code;
• a pulse generator configured to generate an injection signal corresponding to an edge of the second reference clock signal during each period of the second reference clock signal;
• an oscillator configured to generate a local clock signal with a phase synchronized with the injection signal, in response to the injection signal;
• a phase detector configured to generate a phase error value based on a phase difference between the local clock signal and the second reference clock signal;
• a rollover logic circuit configured to output an estimation code based on the phase error value;
• an accumulator configured to output a phase code based on a value obtained by accumulating values represented by phase information received from outside the clock generator;
• a multiplexer configured to output, as the DTC code, the phase code or the estimation code;
• and
• the rollover logic circuit being further configured to provide the estimation code to the accumulator as a rollover code in response to the DTC code matching a bound reference code.

A device comprising:

• a Phase Locked Loop (PLL) configured to generate a first reference clock signal;
• a clock generator configured to generate a local clock signal based on the first reference clock signal;
• and
• a Clock and Data Recovery (CDR) circuit configured to output phase information of the local clock signal based on the local clock signal and data received from outside the CDR,
• wherein the clock generator comprises
• a Digital-to-Time Converter (DTC) configured to output a second reference clock signal by adjusting, based on DTC code, a phase of the first reference clock signal;
• an oscillator configured to generate a local clock signal synchronized to have a rising edge at an edge of the second reference clock signal,
• a phase detector configured to generate a phase error value based on a phase difference between the local clock signal and the second reference clock signal;
• and
• a DTC control circuit configured to output the DTC code based on the phase error value and the phase information,
• wherein, in response to the DTC code matching a bound reference code, the DTC control circuit is further configured to update the DTC code to a rollover target code, and
• the oscillator is further configured to adjust a phase of the second reference clock signal such that the local clock signal has a falling edge at the edge of the second reference clock signal corresponding to the rollover target code.