Clock Generation Circuit With Time Delay Adjustment

A method for generating a clock signal with delay adjustment, comprising:

• receiving a frequency control word at a numerically controlled oscillator;
• generating a fractional time signal based on the frequency control word;
• applying the fractional time signal to a variable delay circuit comprising a buffer driving a variable switch-capacitor network to produce a time delay that is linear with total capacitance at a load using probabilistic delay assignment;
• and
• probabilistically selecting between a first delay implementation using delay line only and a second delay implementation using a sample clock period delay plus delay line, wherein the probabilistic selection uses probabilities p1=m1/L and p2=(L−m1)/L, where m1 represents a fractional portion of a desired delay and L represents a ratio between a sample clock period and a unit delay.

A fractional clock divider circuit, comprising:

• an accumulator configured to maintain a count value based on a frequency control word;
• a comparator configured to generate an output clock signal when the count value drops below a threshold;
• a delay adjustment circuit comprising a switch-capacitor network configured to provide variable time delays that are linear with capacitance;
• and
• a ratio estimation circuit configured to estimate a ratio between a sample clock period and a unit delay by comparing two delay implementations for delays between the sample clock period and twice the sample clock period, wherein a first delay implementation uses delay line only and a second delay implementation uses the sample clock period delay plus delay line.