Multiple channel memory system

A memory system, comprising:

• a memory controller coupled to a memory interface circuit to first and second memory devices, the memory interface circuit comprising:
• first and second memory channels having respective data widths, and configured to couple, respectively, first and second input-output (I/O) interfaces of the memory controller to an interface of the first memory device having a data channel width at least equal to combined first and second memory channel widths, wherein the first and second memory channels have respective associated independent first and second command/address (CA) paths;
• and
• third and fourth memory channels having respective data widths, and configured to couple, respectively, third and fourth I/O interfaces of the memory controller to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have respective associated independent third and fourth CA paths, which are further independent from the first and second memory channel CA paths:
• wherein the memory controller includes one or more processors, and is configured to perform operations including performing a first memory read operation, including,
• providing independent CA signals to a selected channel of the at least four memory channels, through the associated CA path, including,
• at a first time, providing a first row-activate command, followed by a first read command to the selected channel, and
• at a second time, prior to expiration of an activate-to-activate delay interval initiated with the first row-activate command, providing a second read command to the selected channel;
• at a third time, before the second time, receiving a first burst of data responsive to the first row-activate command and the first read command;
• and
• at a fourth time, after the second time, receiving a first burst of data responsive to the first row-activate command and the second read command.

A memory system, comprising:

• a memory controller;
• first and second memory devices configured to couple to an I/O interface of the memory controller, wherein:
• each of the first and second memory devices includes respective first and second independently addressable memory interfaces for providing access to independent portions of each memory device, and
• the I/O interface includes at least four independently addressable memory channels for coupling respective portions of the first and second memory devices to the memory controller, wherein each memory channel includes a respective associated independent command/address (CA) path;
• and
• an interposer configured to couple each independently addressable memory channel to a separate memory interface of the first and second memory devices;
• wherein the first and second memory devices are configured to communicate a specified number of bytes over each independently addressable memory interface for each memory access operation received at the independently addressable memory interface, wherein the first and second memory devices are configured to prefetch twice the specified number of bytes per memory access operation received at the independently addressable memory interface;
• wherein the memory controller includes one or more processors, and is configured to perform memory access operations including performing a first memory read operation, including,
• providing independent CA signals to a selected memory channel of the at least four memory channels, through the associated independent CA path, including,
• at a first time, providing a first row-activate command to the selected memory channel, followed by a first read command:
• at a second time, prior to expiration of an activate-to-activate delay interval, providing a second read command to the selected memory channel;
• at a third time, before the second time, receiving a first burst of data responsive to the first row-activate command and the first read command;
• and
• at a fourth time, after the second time, receiving a first burst of data responsive to the first row-activate command and the second read command.

A system comprising:

• first and second memory devices having common address and command signals, wherein each memory device has a respective first data width, and wherein the first and second devices are configured to collectively provide a memory interface having a second data width, the second data width having twice as many bits as the first data width;
• and
• a memory controller includes one or more processors, and is configured to perform memory access operations including a memory read operation comprising issuing read commands to read data from the first and second memory devices using an I/O interface including four memory channels,
• wherein the memory controller is configured to issue independent command/address (C/A) commands over each memory channel to access independently addressable regions of each memory device, wherein the C/A commands of a first memory read operation in a first memory channel comprise,
• at a first time, providing a first row-activate command to the first memory channel, followed by a first read command, and
• at a second time, prior to expiration of an activate-to-activate delay interval initiated with the first row-activate command, providing a second read command to the first memory channel;
• wherein the memory controller is further configured to receive data responsive to read requests, including:
• at a third time, before the second time, receiving a first burst of data responsive to the first row-activate command and the first read command;
• and
• at a fourth time, after the second time, receiving a first burst of data responsive to the first row-activate command and the second read command.