Bus load monitoring in a memory sub-system controller
AssigneeMicron Technology, Inc.
InventorAndrei Konan
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a memory bus coupled to a random access memory (RAM). A plurality of ports enable hardware logic to access the RAM over the memory bus. A central processing unit (CPU) is coupled to the memory bus. A first hardware logic module is coupled to a first port, of the plurality of ports, to share access to the memory bus with the CPU. A plurality of hardware registers, coupled to the plurality of ports, include a first hardware register to store a number of accesses, by the first hardware logic module, to the memory bus over the first port.
Claims20
An integrated circuit comprising:
- a memory bus coupled to a random access memory (RAM);
- a plurality of ports that enable a plurality of hardware logic modules to access the RAM over the memory bus;
- a central processing unit (CPU) coupled to the memory bus;
- a first hardware logic module, of the plurality of hardware logic modules, coupled to a first port, of the plurality of ports, to share access to the memory bus with the CPU and others of the plurality of hardware logic modules;
- and
- a plurality of hardware registers, coupled to the plurality of ports, comprising a first hardware register to store a number of accesses, by the first hardware logic module, to the memory bus over only the first port.
A system comprising:
- a random access memory (RAM);
- a memory bus coupled to the RAM;
- a plurality of ports that enable hardware logic to access the RAM over the memory bus;
- a plurality of hardware logic modules, each coupled to a port of the plurality of ports, which enables shared access to the memory bus;
- and
- a plurality of hardware registers coupled to the plurality of ports, wherein each hardware register of the plurality of hardware registers is to store a number of accesses by a particular hardware logic module, of the plurality of hardware logic modules, through a particular port of the plurality of ports.
An integrated circuit comprising:
- a memory bus coupled to a random access memory (RAM);
- a plurality of ports that enable hardware logic to access the RAM over the memory bus;
- a plurality of hardware logic modules, each coupled to a port of the plurality of ports, which enables shared access to the memory bus;
- one or more central processing units (CPUs), each of which is coupled to the memory bus;
- and
- a plurality of hardware registers coupled to the plurality of ports, wherein each hardware register of the plurality of hardware registers is to store a number of accesses by a particular hardware logic module, of the plurality of hardware logic modules, through a particular port of the plurality of ports.
Dependencies are inferred from the claim text.