Lane Margin Testing Method and Related Non-Transitory Computer-Readable Storage Medium

Abstract

A lane margin testing method for testing a plurality of Peripheral Component Interconnect Express (PCIe) lanes of an electronic system includes storing test software in a non-transitory computer-readable storage medium of the electronic system; generating a plurality of instruction files based on information of the plurality of PCIe lanes and storing the plurality of instruction files in the non-transitory computer-readable storage medium, wherein each of the plurality of instruction files includes a plurality of test instructions for a corresponding PCIe lane; and generating an auto-run file based on the plurality of instruction files and storing the auto-run file in the non-transitory computer-readable storage medium, wherein the auto-run file is used to instruct the test software to execute the plurality of test instructions recorded in each instruction file of the plurality of instruction files.

Dependencies are inferred from the claim text.