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US 2026/0056856 A1Published application
Systems and methods providing fault injection
AssigneeTexas Instruments Incorporated
InventorsSaya Goud Langadi, Naveen Kothuri
Life of this patent
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Abstract
A system includes fault emulation testing circuitry. The system may implement the fault emulation testing circuitry in a processing core, rather than in an interconnect. The fault emulation testing circuitry may inject a fault into an error correction hash.
Claims20
A method comprising:
- transmitting an information signal from a sending circuit to a receiving circuit;
- calculating a first error correction value of the information signal;
- injecting an error into the first error correction value, thereby generating a second error correction value;
- transmitting the second error correction value to the receiving circuit;
- receiving a result of an error correction check from the receiving circuit;
- and
- determining whether the error has been detected based on the result of the error correction check.
4 more elements
A system comprising:
- a sending circuit, including:
- first sequential logic configured to transmit an information signal;
- an error correction calculator configured to generate a first error correction value based on the information signal;
- a fault injection circuit configured to modify the first error correction value by injecting an error, thereby creating a second error correction value;
- and
- second sequential logic configured to transmit the second error correction value;
- and
- a receiving circuit, coupled to the sending circuit, configured to receive the information signal and the second error correction value, wherein the receiving circuit includes:
- error correction circuitry configured to process the information signal and the second error correction value and to return a result to the sending circuit.
6 more elements
A circuit comprising:
- a first sequential logic circuit configured to transmit an information signal to a receiving circuit;
- an error correction calculator circuit configured to generate a first error correction value based on the information signal;
- a fault injection circuit configured to modify the first error correction value by injecting an error, thereby creating a second error correction value;
- a second sequential logic circuit configured to transmit the second error correction value to the receiving circuit;
- and
- an error detector circuit configured to receive a response from the receiving circuit and to determine whether the error was detected based on the response.
3 more elements
Dependencies are inferred from the claim text.