US 2026/0053015 A1Published application

Semiconductor package

AssigneeSamsung Electronics Co., Ltd.

InventorJitaek Oh

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Abstract

A semiconductor package includes a package substrate including first and second power P-pads and first and second signal P-pads, a lower layer chip including first and second power L-pads and first and second signal L-pads, an upper layer chip offset from the lower layer chip and including first and second power U-pads and first and second signal U-pads. The first power and signal P-pads are alternatingly stacked, the first power and signal L-pads are alternatingly stacked, and the first power and signal U-pads are alternatingly stacked. The second power and signal P-pads are alternatingly stacked, the second power and signal L-pads are alternatingly stacked, and the second power and signal U-pads are alternatingly stacked. Bonding wires connect the first and second power U-pads, the first and second power L-pads, the second power U-pads and P-pads, and the second signal U-pads and P-pads.

Claims20

Dependent claims

A semiconductor package comprising:

a package substrate comprising first power P-pads and second power P-pads configured to transmit power/ground signals and first signal P-pads and second signal P-pads configured to transmit data signals;
a lower layer chip that is on the package substrate and comprises first power L-pads and second power L-pads configured to transmit the power/ground signals and first signal L-pads and second signal L-pads configured to transmit the data signals;
and
an upper layer chip that is on and offset from the lower layer chip in a first direction that is parallel to an upper surface of the package substrate, the upper layer chip comprising first power U-pads and second power U-pads configured to transmit the power/ground signals and first signal U-pads and second signal U-pads configured to transmit the data signals,
wherein, in a first region of the package substrate, the first power P-pads and the first signal P-pads are alternatingly stacked in a second direction that is parallel to the upper surface of the package substrate, the first power L-pads and the first signal L-pads are alternatingly stacked in the second direction, and the first power U-pads and the first signal U-pads are alternatingly stacked in the second direction,
wherein, in a second region of the package substrate that is spaced apart from the first region in the second direction, the second power P-pads and the second signal P-pads are alternatingly stacked in the second direction, the second power L-pads and the second signal L-pads are alternatingly stacked in the second direction, and the second power U-pads and the second signal U-pads are alternatingly stacked in the second direction, and
a plurality of bonding wires that electrically connect the first power U-pads and the second power U-pads and the first power L-pads and the second power L-pads to each other, respectively, the second power U-pads and the second power P-pads to each other, and the second signal U-pads and the second signal P-pads to each other.

4 more elements

A semiconductor package comprising:

a package substrate comprising first power P-pads and second power P-pads configured to transmit power/ground signals, and first signal P-pads and second signal P-pads configured to transmit data signals;
and
first to fourth chips that are stacked on top of each other, offset from each other in a first direction that is perpendicular to an upper surface of the package substrate, and on the package substrate, wherein each of the first to fourth chips comprises first power pads and second power pads configured to transmit the power/ground signals and first signal pads and second signal pads configured to transmit the data signals,
wherein, in a first region of the package substrate, the first power P-pads and the first signal P-pads are alternatingly stacked in a second direction that is parallel to the upper surface of the package substrate, and the first power pads and the first signal pads of each of the first to fourth chips are alternatingly stacked in the second direction,
wherein, in a second region of the package substrate that is spaced apart from the first region in the second direction, the second power P-pads and the second signal P-pads are alternatingly stacked in the second direction, and the second power pads and the second signal pads of each of the first to fourth chips are alternatingly stacked in the second direction, and
a plurality of bonding wires that electrically connect the first power pads and the second power pads of the second to fourth chips to each other, the first power pads and the second power pads of the first to third chips to each other, the second power pads of the second and fourth chips and the second power P-pads to each other, and the second signal pads of the second and fourth chips and the second signal P-pads to each other.

3 more elements

A semiconductor package comprising:

a package substrate comprising a first channel and a second channel, the first channel comprising first power P-pads, second power P-pads, first signal P-pads and second signal P-pads, the second channel comprising first power P-pads, second power P-pads, first signal P-pads and second signal P-pads;
and
first to fourth chips that are stacked on top of each other, offset from each other in a first direction that is perpendicular to an upper surface of the package substrate, and on the package substrate, wherein each of the first to fourth chips comprises first and second power pads configured to transmit power/ground signals and first and second signal pads configured to transmit data signals,
wherein, in a first region of the package substrate, the first power P-pads and the first signal P-pads of the first channel are alternatingly stacked in a second direction that is parallel to the upper surface of the package substrate, the first power P-pads and the first signal P-pads of the second channel are alternatingly stacked in the second direction, and the first power pads and the first signal pads of each of the first to fourth chips are alternatingly stacked in the second direction,
wherein, in a second region of the package substrate that is spaced apart from the first region in the second direction, the second power P-pads and the second signal P-pads of the first channel are alternatingly stacked in the second direction, the second power P-pads and the second signal P-pads of the second channel are alternatingly stacked in the second direction, and the second power pads and second signal pads of each of the first to fourth chips are alternatingly stacked in the second direction, and
a plurality of bonding wires that electrically connect the first power pads and the second power pads of the second to fourth chips and the first power pads and the second power pads of the first to third chips, respectively, to each other, the second power pads of the second chip and the second power P-pads of the first channel to each other, the second power pads of the fourth chip and the second power P-pads of the second channel to each other, the second signal pads of the second chip and the second signal P-pads of the first channel to each other, and the second signal pads of the fourth chip and the second signal P-pads of the second channel to each other.

3 more elements

Dependencies are inferred from the claim text.