Ldmos with bias circuit for biased field plate

A semiconductor device, comprising:

• a drain extended transistor, including:
• a semiconductor layer including a body region having a first conductivity type and a drain drift region having a second, opposite, conductivity type;
• a gate dielectric layer over the body region and extending over a junction between the body region and the drain drift region;
• a gate electrode over the gate dielectric layer;
• a drain region having the second conductivity type in the drain drift region, the drain region having a dopant density greater than a dopant density of the drain drift region;
• and
• a field plate between the gate electrode and the drain region;
• and
• a bias circuit including a clamp circuit with a diode coupled to the field plate.

A semiconductor device, comprising:

• a drain extended transistor, including:
• a semiconductor layer including a body region having a first conductivity type and a drain drift region having a second, opposite, conductivity type;
• a gate dielectric layer over the body region and extending over a junction between the body region and the drain drift region;
• a gate electrode over the gate dielectric layer;
• a drain region having the second conductivity type in the drain drift region, the drain region having a dopant density greater than a dopant density of the drain drift region;
• and
• a field plate between the gate electrode and the drain region;
• and
• a bias circuit coupled to the field plate, the bias circuit including a reset circuit.

A semiconductor device, comprising:

• a drain extended transistor, including:
• a semiconductor layer including a body region having a first conductivity type and a drain drift region having a second, opposite, conductivity type;
• a gate dielectric layer over the body region and extending over a junction between the body region and the drain drift region;
• a gate electrode over the gate dielectric layer;
• a drain region having the second conductivity type in the drain drift region, the drain region having a dopant density greater than a dopant density of the drain drift region;
• and
• a field plate between the gate electrode and the drain region;
• and
• a bias circuit coupled to the field plate, the bias circuit including a second transistor.

A semiconductor device, comprising:

• a drain extended transistor, including:
• a semiconductor layer including a body region having a first conductivity type and a drain drift region having a second, opposite, conductivity type;
• a gate dielectric layer over the body region and extending over a junction between the body region and the drain drift region;
• a gate electrode over the gate dielectric layer;
• a drain region having the second conductivity type in the drain drift region, the drain region having a dopant density greater than a dopant density of the drain drift region;
• and
• field plates spaced apart from one another between the gate electrode and the drain region;
• and
• a bias circuit having outputs coupled to the respective field plates, and an input coupled to one of a voltage input of the semiconductor device, the drain region, and a gate drive circuit.

A method, comprising:

• forming a drain extended transistor in a semiconductor device, the drain extended transistor including:
• a semiconductor layer including a body region having a first conductivity type and a drain drift region having a second, opposite, conductivity type;
• a gate dielectric layer over the body region and extending over a junction between the body region and the drain drift region;
• a gate electrode over the gate dielectric layer;
• a drain region having the second conductivity type in the drain drift region, the drain region having a dopant density greater than a dopant density of the drain drift region;
• and
• a field plate between the gate electrode and the drain region;
• and
• forming a bias circuit in the semiconductor device, the bias circuit including an output coupled to the field plate and a bias input coupled to a gate drive circuit.