Error detection
AssigneeInfineon Technologies AG
InventorsThomas Kern, Alexander Klockmann, Michael Goessel
Life of this patent
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Abstract
Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) the second byte series is permissible if (a) it equals the corresponding byte of the first byte sequence or (b) an error being a member of a predetermined error set could cause the byte of the second byte sequence to become the byte of the first byte sequence, and otherwise (c) the byte of the second byte sequence is impermissible, and (iii) at least one error is detected if the second byte sequence is impermissible.
Claims20
A method for error detection, comprising:
- reading a first byte sequence of n-bit bytes from memory;
- transforming the first byte sequence into a sequence of k-bit bytes using a transformation T−1;
- carrying out a transformation T, the inverse of transformation T−1, to obtain a second byte sequence of n-bit bytes;
- determining that a byte of the second byte sequence is permissible if (a) it equals the corresponding byte of the first byte sequence or (b) an error being a member of a predetermined error set could cause the byte of the second byte sequence to become the byte of the first byte sequence, and otherwise (c) determining that the byte of the second byte sequence is impermissible, and
- in response to determining that at least one byte of the second byte sequence is impermissible, providing indication of a false error correction.
A device for error detection comprising
- a corrector configured to transform a first byte sequence of n-bit bytes read from a memory into a sequence of k-bit bytes using a transformation T−1;
- and
- a checking unit configured to
- carry out a transformation T, the inverse of transformation T−1, to obtain a second byte sequence of n-bit bytes,
- determine that a byte of the second byte sequence is permissible if (a) it equals the corresponding byte of the first byte sequence or (b) an error being a member of a predetermined error set could cause the byte of the second byte sequence to become the byte of the first byte sequence, and otherwise (c) determining that the byte of the second byte sequence is impermissible;
- and
- detect a false correction in response to the second byte sequence being determined as impermissible.
A false error correction detection system, comprising:
- a memory;
- a decoder coupled to the memory, configured to transform a first byte sequence of n-bit bytes read from the memory into a sequence of k-bit bytes using a transformation T−1;
- an encoder coupled to the memory and an output of the decoder, configured to carry out a transformation T, the inverse of transformation T−1, to obtain a second byte sequence of n-bit bytes;
- and
- a comparator coupled to the memory and the encoder, configured to
- determine that a byte of the second byte sequence is permissible if (a) it equals the corresponding byte of the first byte sequence or (b) an error being a member of a predetermined error set could cause the byte of the second byte sequence to become the byte of the first byte sequence, and otherwise (c) determining that the byte of the second byte sequence is impermissible;
- and
- in response to determining that at least one byte of the second byte sequence is impermissible, providing indication of a false error correction.
Dependencies are inferred from the claim text.