Apparatuses and methods for configurable ecc modes
AssigneeMicron Technology, Inc.
InventorsScott E. Smith, Sujeet Ayyapureddi
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.
Claims20
An apparatus comprising:
- a first data column plane comprising a first bit line;
- a second data column plane comprising a second bit line;
- an extra column plane comprising a third bit line;
- and
- an error correction code (ECC) circuit configured to, as part of an access operation:
- access data bits along the first bit line,
- in a first mode, access additional data bits along the second bit line and error correction (EC) bits along the third bit line, and
- in a second mode, access the EC bits along an activated one of the second bit line, the third bit line, or a combination thereof.
An apparatus comprising:
- a first plurality of column planes and a second plurality of column planes, both configured to store data bit and error correction (EC) bits;
- and
- an extra column plane configured to store EC bits,
- wherein as part of an access operation, data bits are accessed in the first plurality of column planes, wherein in a first mode, additional data bits are accessed in the second plurality of column planes and EC bits are accessed in the extra column plane, and wherein in a second mode, EC bits are accessed in the second plurality of column planes, the extra column plane, or a combination thereof.
A method comprising:
- receiving a column address as part of an access operation, wherein the column address includes a value indicative of a first mode or a second mode;
- accessing data bits from columns in a first plurality of data column planes as part of the access operation based on the column address;
- accessing additional data bits from columns in a second plurality of data column planes and Error Correction (EC) bits in an extra column plane in the first mode;
- and
- accessing EC bits in the columns in the second plurality of data column planes, the extra column plane, or a combination thereof in the second mode.
Dependencies are inferred from the claim text.