Providing processor core fault recovery without requiring system resets in multicore processor-based devices

A processor-based device, comprising:

• means for receiving an interrupt corresponding to a registered timer event from a timer peripheral circuit;
• means for transmitting an interprocess interrupt (IPI) to a processor core of a plurality of processor cores of the processor-based device, responsive to receiving the interrupt;
• means for determining whether a status update was successfully received from the processor core in response to the IPI;
• means for performing one or more migration operations on the processor core, responsive to determining that a status update was not successfully received from the processor core;
• means for masking the processor core as offline for scheduling purposes, further responsive to determining that a status update was not successfully received from the processor core;
• and
• means for blocking the processor core from further health monitoring, further responsive to determining that a status update was not successfully received from the processor core.

A method for providing processor core fault recovery in multicore processor-based devices, the method comprising:

• receiving, by a first processor core, configured to operate as a bootstrap processor core (BSP), of a plurality of processor cores of a processor-based device, an interrupt corresponding to a registered timer event from a timer peripheral circuit;
• responsive to receiving the interrupt, transmitting, by the first processor core, an interprocess interrupt (IPI) to a second processor core of the plurality of processor cores;
• determining, by the first processor core, that a status update was not successfully received from the second processor core in response to the IPI;
• and
• responsive to determining that a status update was not successfully received from the second processor core:
• performing, by the first processor core, one or more migration operations on the second processor core;
• masking, by the first processor core, the second processor core as offline for scheduling purposes;
• and
• blocking, by the first processor core, the second processor core from further health monitoring.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor device to:

• receive an interrupt corresponding to a registered timer event from a timer peripheral circuit;
• transmit an interprocess interrupt (IPI) to a processor core of a plurality of processor cores of the processor device, responsive to receiving the interrupt;
• determine whether a status update was successfully received from the processor core in response to the IPI;
• and
• responsive to determining that a status update was not successfully received from the processor core:
• perform one or more migration operations on the processor core;
• mask the processor core as offline for scheduling purposes;
• and
• block the second processor core from further health monitoring.