Power timing control device and method

A power timing control device, comprising:

• a power conversion unit configured to generate a DC power voltage;
• a primary chip configured to generate at least one primary enable signal based on the DC power voltage;
• and
• one or more controlled chips, wherein each of the one or more controlled chips is coupled to the power conversion unit and the primary chip, and comprises:
• an auxiliary circuit configured to generate an auxiliary enable signal based on the DC power voltage;
• and
• a controlled circuit configured to be enabled based on a logical-AND-gated operation of the primary enable signal and the auxiliary enable signal to generate a control voltage based on the DC power voltage;
• wherein in a signal timing sequence, a representative moment during the control voltage falling from a high level to a low level occurs earlier than a moment when a level on a signal waveform of the DC power voltage falling from the high level to the low level equals a minimum operation voltage level for the controlled chip.

A power timing control method, applied to a circuit comprising a power conversion unit, a primary chip, one or more auxiliary chips, and one or more controlled chips, wherein each of the one or more controlled chips is coupled to the power conversion unit, a respective one of the one or more auxiliary chips, and the primary chip, and the method comprises:

• enabling the power conversion unit to generate a DC power voltage;
• enabling the primary chip to generate at least one primary enable signal based on the DC power voltage;
• enabling each of the one or more auxiliary chips to generate an auxiliary enable signal based on the DC power voltage;
• and
• controlling each of the one or more controlled chips to be enabled based on a logical-AND-gated operation of the primary enable signal and the auxiliary enable signal to generate a control voltage based on the DC power voltage;
• wherein in a signal timing sequence, a representative moment during the control voltage falling from a high level to a low level occurs earlier than a moment when a level on a signal waveform of the DC power voltage falling from the high level to the low level equals a minimum operation voltage level for the controlled chip.