Test circuit for reliability test of device under test and method for operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorSZU-CHUN TSAO
Life of this patent
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Abstract
The present disclosure provides an integrated circuit, which includes a device under test (DUT) and a test circuit. The test circuit includes a clock generator, a gate control circuit, and a gate isolation circuit. The clock generator is configured to generate a clock signal. The gate control circuit is configured to convert, in response to a test enable signal being deasserted, the clock signal within a first voltage domain to generate a gate clock signal within a second voltage domain at an output terminal of the gate control circuit which is connected to a gate terminal of the DUT. The gate isolation circuit is coupled between the gate terminal of the DUT and a first input/output (I/O) pad of the integrated circuit.
Claims20
An integrated circuit, comprising:
- a device under test (DUT);
- and
- a test circuit, comprising:
- a clock generator, configured to generate a clock signal;
- a gate control circuit, configured to convert, in response to a test enable signal being deasserted, the clock signal within a first voltage domain to generate a gate clock signal within a second voltage domain at an output terminal of the gate control circuit which is connected to a gate terminal of the DUT;
- and
- a gate isolation circuit, coupled between the gate terminal of the DUT and a first input/output (I/O) pad of the integrated circuit.
An integrated circuit, comprising:
- a device under test (DUT), comprising a gate terminal, a first terminal, and a second terminal;
- and
- a test circuit, comprising:
- a gate control circuit, configured to switch to a high-impedance state at an output terminal of the gate control circuit which is connected to a gate terminal of the DUT in response to a test enable signal being asserted;
- and
- a gate isolation circuit, coupled between the gate terminal of the DUT and a first input/output (I/O) pad of the integrated circuit,
- wherein the first terminal and the second terminal of the DUT are coupled to a second I/O pad and a third I/O pad of the integrated circuit.
A method, comprising:
- providing a first voltage to a first I/O pad, a second I/O pad, and a third I/O pad of an integrated circuit, wherein the first I/O pad is electrically connected to a gate terminal of a device under test (DUT) through a resistor, and the second I/O pad and the third I/O pad are connected to a first terminal and a second terminal of the DUT, respectively;
- measuring a first leakage current through the first I/O pad;
- providing a ground voltage to the second I/O pad and the third I/O pad;
- measuring a second leakage current through the first I/O pad;
- and
- calculating a gate leakage current of the DUT by subtracting the first leakage current from the second leakage current.
Dependencies are inferred from the claim text.