Back to results
US 2026/0046472 A1Published application
Display driving apparatus, and display apparatus having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsTaehong Kim, Joohee Choi, Dayoung Kim, Soyoung Shin
Life of this patent
Estimating the term…
Abstract
A display apparatus includes: a video processing unit processing a video signal; a graphics processing unit processing a graphics signal; a mixing unit mixing video corresponding to the processed video signal and graphics corresponding to the processed graphics signal; a display unit outputting the mixed video and graphics; and a main processing unit configured to control the video processing unit, the graphics processing unit, the mixing unit and the display unit.
Claims20
A display apparatus, comprising:
- a video processor configured to process a video signal;
- a graphics processor configured to process a graphics signal;
- a mixing processor configured to mix the processed video signal and the processed graphics signal to provide a mixed video and graphics signal;
- a display device configured to output the mixed video and graphics signal;
- and
- a main processor configured to control the video processor, the graphics processor, the mixing processor, and the display device,
- wherein the video signal includes a plurality of video frames, and the graphics signal includes a plurality of graphics frames, and
- wherein the main processor is configured to
- calculate, for each video frame of the plurality of video frames, a respective video delay time using both a video rendering request time at which rendering is requested for the video frame and a video output time at which the video frame is output to the display device,
- calculate, for each graphics frame of the plurality of graphics frames, a respective graphics delay time using both a graphics rendering request time at which rendering is requested for the graphics frame and a graphics output time at which the graphics frame is output to the display device, and
- synchronize the plurality of video frames and the plurality of graphics frames by compensating at least one video delay time, at least one graphics delay time, or at least one video delay time and at least one graphics delay time.
8 more elements
A display apparatus, comprising:
- a video processor configured to process a video signal including a plurality of video frames, the video processor including a plurality of video processing components;
- a graphics processor configured to process a graphics signal that includes a plurality of graphics frames, the graphics processor including a plurality of graphics processing components;
- a mixing processor configured to mix the processed video signal and the processed graphics signal to provide a mixed video and graphics signal;
- a display device configured to output the mixed video and graphics signal;
- and
- a main processor configured to control the video processor, the graphics processor, the mixing processor, and the display device,
- wherein a number of the plurality of video processing components is greater than a number of the plurality of graphics processing components, and
- wherein the main processor is configured to
- shorten, for each of the plurality of video frames, a respective video delay time using a time at which each of the plurality of video frames is output to the display device, or
- extend, for each graphics frame of the plurality of graphics frames, a respective graphics delay time using a time at which each of the plurality of graphics frames is output to the display device.
7 more elements
A display driving apparatus, comprising:
- a first semiconductor chip including a first video processor configured to process a video signal including a plurality of video frames, a first graphics processor configured to process a graphics signal including a plurality of graphics frames, a first main processor configured to control the first video processor and the first graphics processor, and a first memory circuit including a first video buffer configured for storing the processed video signal and a first graphics buffer for storing the processed graphics signal;
- and
- a second semiconductor chip including a second video processor configured to process the processed video signal, a second graphics processor configured to process the processed graphics signal, a second main processor configured to control the second video processor and the second graphics processor, and a second memory circuit including a second video buffer configured to store the processed video signal and a second graphics buffer configured to store the processed graphics signal,
- wherein the first main processor is configured to
- calculate, for each of the plurality of video frames, a respective video delay time using a time at which each of the plurality of video frames is output, and
- calculate, for each of the plurality of graphics frames, a respective graphics delay time using a time at which each of the plurality of graphics frames is output, and
- wherein the first main processor and the second main processor are configured to
- shorten the video delay time by omitting at least portions of a plurality of first video processing components included in the first video processor and a plurality of second video processing components included in the second video processor, or
- extend the graphics delay time by including a graphics buffer to at least one of the first graphics buffer and the second graphics buffer.
6 more elements
Dependencies are inferred from the claim text.