Wafer level package

A wafer level package, comprising:

• a substrate having a functional layer and electric device structures realized in the functional layer, on the functional layer, or under the functional layer;
• a first package layer applied on the substrate, the first package layer defining cavities between the substrate and the first package layer, at least part of the electric device structures being arranged in the cavities;
• a second package layer applied over a surface of the first package layer;
• pads arranged on the substrate and connected to the electric device structures, a partial area of each pad forming a respective contact area that is not covered by the first package layer or the second package layer;
• and
• an interconnect structure deposited on each respective contact area and extending up to an interconnected height (hi) over the substrate, the interconnected height being higher than a package height (hp) of the first package layer and the second package layer over the substrate;
• wherein a plurality of gaps are disposed between edges of the first package layer and respective circumferences of respective interconnect structures surrounded by corresponding edges of the first package layer.

A wafer level package, comprising:

• a substrate having a functional layer and electric device structures realized in the functional layer, on the functional layer or under the functional layer;
• a plurality of pads arranged on the substrate and each connected to at least one of the electric device structures, a partial area of each pad forming a respective contact area;
• a first package layer applied on the substrate, the first package layer extending partially over at least one pad of the plurality of pads,
• a second package layer extending over a surface of the first package layer and extending partially over the at least one pad;
• and
• an interconnect structure deposited on each respective contact area, wherein a distance between a center of the interconnect structure and the second package layer is less than a distance between the center of the interconnect structure and the first package layer.