Panel-level formation of logic-uppermost semiconductor device assemblies with multi-reticle dies and reticle-bridging conductors

A semiconductor device assembly, comprising:

• a redistribution layer (RDL) including:
• an external surface including a plurality of external contacts,
• an internal surface including a plurality of internal contacts, and
• a plurality of conductors operably coupling individual ones of the plurality of internal contacts to individual ones of the plurality of external contacts;
• a device connection layer including:
• a first surface having a first plurality of contact pads,
• a second surface opposite the first surface and having a second plurality of contact pads,
• a first plurality of conductive structures electrically coupling each of the first plurality of contact pads to a corresponding contact pad of the second plurality of contact pads, and
• a second plurality of conductive structures electrically coupling each of a first subset of the second plurality of contact pads to a corresponding contact pad of a second subset of the second plurality of contact pads;
• and
• a plurality of stacks of semiconductor devices disposed between the RDL and the device connection layer, each stack disposed in a cavity in a monolithic glass structure, the plurality of stacks electrically coupling individual ones of the plurality of internal contacts to individual ones of the first plurality of contact pads through TSVs disposed in the plurality of stacks.

A method of making a semiconductor device assembly, comprising:

• providing a glass panel with a plurality of cavities;
• disposing a plurality of stacks of semiconductor devices in the plurality of cavities;
• forming a device connection layer over the glass panel and the plurality of stacks of semiconductor devices, the device connection layer including a first surface having a first plurality of contact pads operably connected to the plurality of stacks of semiconductor devices, a second surface opposite the first surface and having a second plurality of contact pads, a first plurality of conductive structures electrically coupling each of the first plurality of contact pads to a corresponding contact pad of the second plurality of contact pads, and a second plurality of conductive structures electrically coupling each of a first subset of the second plurality of contact pads to a corresponding contact pad of a second subset of the second plurality of contact pads;
• and
• forming a redistribution layer (RDL) including an external surface including a plurality of external contacts, an internal surface including a plurality of internal contacts operably connected to the plurality of stacks of semiconductor devices, and a plurality of conductors operably coupling individual ones of the plurality of internal contacts to individual ones of the plurality of external contacts.