Interposer, semiconductor package including interposer and method for manufacturing the same

An interposer comprising:

• a first redistribution structure;
• a bridge die on the first redistribution structure;
• a plurality of conductive posts adjacent the bridge die and on the first redistribution structure;
• a second redistribution structure on the bridge die and the plurality of conductive posts;
• and
• a molding material between the first redistribution structure and the second redistribution structure so as to at least partially cover the bridge die and the plurality of conductive posts,
• wherein the first redistribution structure includes:
• a dielectric layer;
• a plurality of UBM pads in the dielectric layer;
• a plurality of first vias on the plurality of UBM pads and in the dielectric layer;
• a plurality of redistribution lines on the plurality of first vias and in the dielectric layer;
• a plurality of second vias on the plurality of redistribution lines and in the dielectric layer;
• a plurality of third vias on the plurality of redistribution lines, in the dielectric layer, and adjacent the plurality of second vias;
• a plurality of first bonding pads on the dielectric layer and the plurality of second vias with each of the plurality of first bonding pads connected to the bridge die;
• and
• a plurality of second bonding pads on the dielectric layer and the plurality of third vias and adjacent the plurality of first bonding pads, with each of the plurality of second bonding pads connected to a corresponding conductive post of the plurality of conductive posts, and
• the number of first vias disposed between each of the plurality of UBM pads and a corresponding redistribution line of the plurality of redistribution lines is two or more, and
• the number of second vias disposed between each of the plurality of redistribution lines and a corresponding first bonding pad of the plurality of first bonding pads is two or more, and
• the number of third vias disposed between each of the plurality of redistribution lines and a corresponding second bonding pad of the plurality of second bonding pads is one.

A semiconductor package comprising:

• a redistribution layer interposer;
• a first semiconductor die on the redistribution layer interposer;
• and
• a second semiconductor die adjacent the first semiconductor die and on the redistribution layer interposer,
• wherein the redistribution layer interposer includes:
• a first redistribution structure;
• a bridge die on the first redistribution structure;
• a plurality of conductive posts adjacent the bridge die and on the first redistribution structure;
• a second redistribution structure on the bridge die and the plurality of conductive posts;
• and
• a molding material between the first redistribution structure and the second redistribution structure and at least partially covering the bridge die and the plurality of conductive posts, and
• the first redistribution structure includes:
• a dielectric layer;
• a plurality of redistribution lines in the dielectric layer;
• a plurality of vias on the plurality of redistribution lines and in the dielectric layer;
• a plurality of first bonding pads on the dielectric layer and the plurality of vias and each of the plurality of first bonding pads is connected to the bridge die;
• and
• a plurality of second bonding pads on the dielectric layer and the plurality of vias and adjacent the plurality of first bonding pads, and each of the plurality of second bonding pads is connected to a corresponding conductive post of the plurality of conductive posts, and
• the number of vias disposed between each of the plurality of redistribution lines and a corresponding first bonding pad of the plurality of first bonding pads is two or more, and
• the number of vias disposed between each of the plurality of redistribution lines and a corresponding second bonding pad of the plurality of second bonding pads is one.