Package-package interconnection for solder joint fail redundancy and high bandwidth application

A semiconductor device assembly, comprising:

• a first semiconductor device package and a second semiconductor device package, each compromising one or more semiconductor dice and a package substrate disposed below corresponding one or more semiconductor dice;
• a redistribution layer (RDL) on which the first and the second semiconductor device packages are disposed, the RDL comprises one or more metal traces;
• and
• a first ball grid array (BGA) comprising a first plurality of solder balls corresponding to the first semiconductor device package and a second BGA comprising a second plurality of solder balls corresponding to the second semiconductor device package, wherein the first BGA and the second BGA are disposed under the RDL,
• wherein the one or more metal traces electrically connect one or more solder balls of the first BGA to one or more solder balls of the second BGA.

A method of semiconductor device assembly, comprising:

• forming a plurality of semiconductor device packages, each of the plurality of semiconductor device packages comprising a plurality of contact pads on its frontside surface;
• bonding the plurality of semiconductor device packages to a carrier wafer, wherein a backside surface of each of the plurality of semiconductor device packages is attached to the carrier wafer;
• molding the plurality of semiconductor device packages on the carrier wafer;
• forming a redistributing layer (RDL) above the plurality of contact pads of the plurality of semiconductor device packages;
• fabricating solder balls on the RDL;
• and
• singulating the plurality of semiconductor device packages and debonding the carrier wafer.