Wafer with semiconductor devices and integrated electronic discharge protection

A method, comprising:

• forming a channel layer in a substrate;
• and
• forming high resistivity regions in the substrate to define a first active region in the substrate, a second active region in the substrate, a first portion of the channel layer, a second portion of the channel layer, and a third portion of the channel layer, wherein the first active region includes the first portion of the channel layer, the second active region includes the second portion of the channel layer, the third portion of the channel layer is between the first active region and the second active region, and the first portion of the channel layer is electrically isolated from the third portion of the channel layer;
• forming a dielectric layer over the first portion, second portion, and third portion of the channel layer;
• and
• forming a conductive via pad that extends over the dielectric layer, connecting a back metal layer through a high resistivity region separating the first portion of the channel layer and the second portion of the channel layer.