US 2026/0040936 A1 · SEMICONDUCTOR PACKAGE INCLUDING INTERCONNECT STRUCTURES

Abstract

A semiconductor package includes a lower interconnect structure. The lower interconnect structure includes a lower insulating layer and lower interconnect patterns. A first encapsulation layer is disposed on the lower interconnect structure. A pillar electrode penetrating the first encapsulation layer and connected to the lower interconnect patterns is provided. An upper interconnect structure disposed within the first encapsulation layer and having an upper insulating layer and upper interconnect patterns is provided. A distance between an upper surface of the lower interconnect structure and an uppermost end of the first encapsulation layer is larger than a distance between the upper surface of the lower interconnect structure and an uppermost end of the upper interconnect structure. A second encapsulation layer is disposed on the first encapsulation layer. A semiconductor chip disposed within the second encapsulation layer and connected to the pillar electrode and upper interconnect patterns is provided.

Claims20

Dependent claims

A semiconductor package comprising:

a lower interconnect structure comprising a lower insulating layer and a plurality of lower interconnect patterns;
a first encapsulation layer on the lower interconnect structure;
a pillar electrode penetrating the first encapsulation layer and connected to the plurality of lower interconnect patterns;
an upper interconnect structure disposed within the first encapsulation layer and comprising an upper insulating layer and a plurality of upper interconnect patterns, a first distance between an upper surface of the lower interconnect structure and an uppermost end of the first encapsulation layer and a second distance between the upper surface of the lower interconnect structure and an uppermost end of the upper interconnect structure, the first distance being larger than the second distance;
a second encapsulation layer on the first encapsulation layer;
and
a semiconductor chip disposed within the second encapsulation layer, the semiconductor chip connected to the pillar electrode and the plurality of upper interconnect patterns.

4 more elements

A semiconductor package comprising:

a lower interconnect structure comprising a lower insulating layer and a plurality of lower interconnect patterns;
a first encapsulation layer on the lower interconnect structure;
a plurality of pillar electrodes penetrating the first encapsulation layer and connected to the plurality of lower interconnect patterns;
an upper interconnect structure disposed within the first encapsulation layer and comprising an upper insulating layer and a plurality of upper interconnect patterns, a first distance between an upper surface of the lower interconnect structure and an uppermost end of the first encapsulation layer and a second distance between the upper surface of the lower interconnect structure and an uppermost end of the upper interconnect structure, the first distance being larger than the second distance;
a second encapsulation layer on the first encapsulation layer;
and
first and second semiconductor chips disposed within the second encapsulation layer, the first and second semiconductor chips connected to the plurality of pillar electrodes and the plurality of upper interconnect patterns.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor package including interconnect structures

Life of this patent

Semiconductor package including interconnect structures

Life of this patent

Abstract

Claims20