Interconnection structure and method of forming the same

A method of forming an interconnection structure, comprising:

• providing a substrate, comprising a lower voltage device region and a higher voltage device region;
• forming a first dielectric layer on the substrate in the lower voltage device region and the higher voltage device region;
• forming an under-layer interconnection structure in the first dielectric layer in the lower voltage device region and the higher voltage device region;
• forming a second dielectric layer on the first dielectric layer in the lower voltage device region and the higher voltage device region;
• forming a first trench and a second trench in the second dielectric layer, wherein the first trench is located in the lower voltage device region, and the second trench is in the higher voltage device region;
• forming a U-shaped high k layer on a bottom surface and sidewalls of the second trench;
• etching a bottom of the first trench to form a first via exposing the under-layer interconnection structure;
• and
• filling the first via, the first trench, and the second trench with a conductive material to respectively form a first via plug, a first metal layer, and a second metal layer,
• wherein a bottom surface of the U-shaped high k layer and a bottom surface of the first metal layer are at a same level in a stacking direction.

An interconnection structure, comprising:

• a substrate, comprising a lower voltage device region and a higher voltage device region;
• a first dielectric layer, located on the substrate in the lower voltage device region and the higher voltage device region;
• an under-layer interconnection structure, located in the first dielectric layer in the lower voltage device region and the higher voltage device region;
• a second dielectric layer, located on the first dielectric layer in the lower voltage device region and the higher voltage device region;
• a first via plug and a first metal layer, located in the second dielectric layer in the lower voltage device region;
• and
• a U-shaped high k layer and a second metal layer, located in the second dielectric layer in the higher voltage device region,
• wherein the U-shaped high k layer surrounds a bottom surface and sidewalls of the second metal layer, and
• a bottom surface of the U-shaped high k layer is higher than a bottom surface of the first metal layer in a stacking direction.

A method of forming an interconnection structure, comprising:

• providing a substrate, comprising a lower voltage device region and a higher voltage device region;
• forming a first dielectric layer on the substrate in the lower voltage device region and the higher voltage device region;
• forming an under-layer interconnection structure in the first dielectric layer in the lower voltage device region and the higher voltage device region;
• forming a second dielectric layer on the first dielectric layer in the lower voltage device region and the higher voltage device region;
• forming an elongated via in the second dielectric layer in the lower voltage device region;
• removing the second dielectric layer around an upper half part of the elongated via to form a first via and a first trench located above the first via;
• forming a second trench in the second dielectric layer in the higher voltage device region;
• forming a U-shaped high k layer on a bottom surface and sidewalls of the second trench;
• and
• filling the first via, the first trench, and the second trench with a conductive material to respectively form a first via plug, a first metal layer, and a second metal layer,
• wherein a bottom surface of the U-shaped high k layer is higher than a bottom surface of the second metal layer in a stacking direction.