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US 2026/0040932 A1Published application
Self-aligned silicide for backside contact
AssigneeQUALCOMM Incorporated
InventorsShreesh NARASIMHA, Yan SUN
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Abstract
The chip includes a first epitaxial (epi) layer, a second epi layer, a gate between the first epi layer and the second epi layer, and one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate. The chip also includes a first salicide layer formed on a bottom surface of the first epi layer.
Claims20
A chip, comprising:
- a first epitaxial (epi) layer;
- a second epi layer;
- a gate between the first epi layer and the second epi layer;
- one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate;
- and
- a first salicide layer formed on a bottom surface of the first epi layer.
3 more elements
A method for processing a chip, wherein the chip includes a first epitaxial (epi) layer and a second epi layer formed on a semiconductor substrate, the method comprising:
- removing most or all of the semiconductor substrate, wherein a bottom surface of the first epi layer and a bottom surface of the second epi layer are exposed after removal of most or all of the semiconductor substrate;
- depositing a metal layer on a backside of the chip, wherein the metal layer covers the bottom surface of the first epi layer and the bottom surface of second epi layer;
- and
- heating the chip, wherein the heating causes the metal layer to react with silicon in the first epi layer to form a first silicide layer and react with silicon in the second epi layer to form a second silicide layer.
1 more element
Dependencies are inferred from the claim text.