Rivet structure and method
AssigneeMicron Technology, Inc.
InventorsMatthew J. King, David H. Wells, Tyler List, Tom J. John, Mojtaba Asadirad
Life of this patent
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Abstract
Semiconductor devices and methods are disclosed, including memory cells/memory strings, semiconductor devices and systems. Example semiconductor devices and methods include a stack of alternating dielectric layers and conductor layers, and a vertical conductor passing between a top level of the stack and a bottom level of the stack. Lateral connections are included between a location along the vertical conductor and a selected conductor layer from the stack, wherein a direct interface is formed between the vertical conductor and the selected conductor layer.
Claims21
A memory device, comprising;
- a stack of alternating dielectric layers and conductor layers;
- a number of liner interface material layers between the conductor layers and the dielectric layers;
- a number of memory cells formed within the stack of alternating dielectric layers and conductor layers;
- a vertical conductor passing between a top level of the stack and a bottom level of the stack;
- a lateral connection between a location along the vertical conductor and a selected conductor layer from the stack, wherein a direct interface is formed between the vertical conductor and the selected conductor layer;
- and
- a lateral isolation structure around the vertical conductor adjacent to at least one other conductor layer from the stack.
A memory device, comprising;
- a stack of alternating dielectric layers and conductor layers;
- a number of liner interface material layers between the conductor layers and the dielectric layers;
- a number of memory cells formed within the stack of alternating dielectric layers and conductor layers;
- a vertical conductor between a top level of the stack and a selected conductor layer from the stack;
- a lateral connection between the vertical conductor and a selected conductor layer from the stack, the lateral conductor forming a direct interface with the selected conductor layer;
- and
- a lateral isolation structure around the vertical conductor adjacent to at least one other conductor layer from the stack.
A method of forming a memory device, comprising;
- forming a staircase in a stack of alternating dielectric layers and placeholder layers;
- forming an etch selective layer on a tread of the staircase;
- filling the staircase with dielectric material to a top surface of the stack;
- forming a passage between the top surface of the stack and a bottom of the stack;
- replacing a portion of the placeholder layers to form one or more lateral isolation structures around the passage, below the etch selective layer;
- replacing a remaining portion of the placeholder layers with a liner material and a first conductor material to form lined conductor layers;
- removing the etch selective layer to form a lateral cavity and removing an exposed portion of the liner material;
- and
- filling the lateral cavity and the passage with a second conductor to form a direct interface with a selected conductor layer adjacent to the lateral cavity.
Dependencies are inferred from the claim text.