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AssigneeAdeia Semiconductor Bonding Technologies Inc.
InventorsGaius Gillman Fountain, JR., Cyprian Emeka Uzoh, George Carlton Hudson, John Posthill
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A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.
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A method of forming a microelectronic structure, the method comprising:
The method of claim 43, further comprising providing a dielectric layer on the bulk semiconductor portion, the dielectric layer at least partially defining the back surface of the substrate, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from the back surface of the substrate.
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The method of claim 49, further comprising preparing the dielectric layer for direct bonding to another element.
A method of forming a microelectronic structure, the method comprising:
The method of claim 60, wherein refilling the portion of the opening with the filling structure comprises providing a second conductive via portion in the opening over the first conductive via portion from the back surface.
The method of claim 61, further comprising recessing the first conductive portion after revealing to define the portion of the opening.
The method of claim 69, further comprising planarizing the second backside dielectric layer and recessing the first conductive via portion relative to the second backside dielectric layer.
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A method of forming a microelectronic structure, the method comprising:
The method of claim 74, wherein removing the portion of the substrate comprises at least one of grinding or polishing the second side.
The method of claim 74, wherein removing the portion of the conductive via comprises etching the conductive via.
The method of claim 75, wherein at least one of grinding or polishing comprises planarizing the substrate and the conductive via.
Dependencies are inferred from the claim text.