US 2026/0040918 A1Published application

Bit line and source line connections for a 3-dimensional array of memory circuits

AssigneeSunrise Memory Corporation

InventorsShohei Kamisaka, Yosuke Nosho

Life of this patent

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Abstract

A conductor-filled via formed in a staircase structure that is provided in conjunction with a 3-dimensional array of memory strings, where the staircase structure includes multiple steps with each step including a bit line layer and a source line layer. The conductor-filled via includes a conductor to electrically connect a top layer in a first step in the staircase structure to a buried contact provided under the staircase structure, the top layer being the bit line layer or the source line layer of the first step; and a spacer insulator lining the sidewalls of the conductor-filled via to isolate the conductor from at least a bottom layer of the first step and the bit line layer or the source line layer in any steps between the first step and the buried contact.

Claims20

Dependent claims

A conductor-filled via formed in a staircase structure that is provided in conjunction with a 3-dimensional array of memory strings formed above a planar surface of a semiconductor substrate, the 3-dimensional array of memory strings comprising a plurality of layers, formed one on top of another and being isolated from each other by a first isolation layer, each layer comprising a drain layer and a source layer isolated from each other by a second isolation layer, the staircase structure comprising a plurality of steps corresponding to the plurality of layers, each step comprising a bit line layer corresponding to the drain layer and a source line layer corresponding to the source layer, the conductor-filled via comprising:

a conductor to electrically connect a top layer in a first step of the plurality of steps in the staircase structure to a buried contact provided under the staircase structure and above the planar surface of the semiconductor substrate, the top layer being the bit line layer or the source line layer of the first step;
and
a spacer insulator lining the sidewalls of the conductor-filled via to isolate the conductor from at least a bottom layer of the first step and the bit line layer or the source line layer in any steps between the first step and the buried contact, the bottom layer of the first step being the bit line layer or the source line layer of the first step other than the top layer,
wherein (i) the first step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate and at least partially overlapping the buried contact along a second direction substantially parallel to the planar surface of the semiconductor substrate;
(ii) the conductor-filled via is formed in a third isolation layer provided adjacent the first step in the second direction and at least partially overlapping the buried contact;
and (iii) the conductor electrically contacts the top layer of the first step.

3 more elements

A process, comprising:

providing a one or more buried contacts above a planar surface of a semiconductor substrate;
creating a staircase structure in conjunction with a 3-dimensional array of memory strings formed above the buried contacts, the staircase structure comprising a plurality of steps formed one on top of another, wherein (i) each step being aligned to one of the buried contacts along a first direction substantially normal to the planar surface and at least partially overlapping the buried contact along a second direction substantially parallel to the planar surface of the semiconductor substrate;
and (ii) each step comprises a plurality of layers, including a bit line layer, a source line layer and a first isolation layer between the source line layer and the bit line layer, the bit line layer or the source line layer forming a top layer of each step;
providing a second isolation layer over the staircase structure;
creating a trench at each step that extends along the first direction through the second isolation layer and the step to the buried contact;
depositing a spacer insulator in each trench and etching back the spacer insulator, so as to expose a portion of the layer at the top layer of each step and the buried contact and so that the spacer insulator lines sidewalls of the trench between the top of each step and the exposed buried contact;
and
filling each trench with a conductor, the conductor being in electrical contact with the top layer of the respective step and the respective buried contact.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/351,839Filed 7 Oct 2025
Priority: 21 Dec 2020
Published: 5 Feb 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 20/062
Of conductive parts of the interconnections: by smoothing of conductive parts, e.g. by planarisation
H10W 20/0698
Of conductive parts of the interconnections: local interconnections

Family

Application63/128,347Us provisional application · filed 21 Dec 2020
Application17/548,034Continuation · filed 10 Dec 2021
Application19/351,839Continuation
US 12,463,138 B2Related patent
US 2022/0199532 A1Published application
US 2026/0040918 A1This patent

From the US filing history. Foreign family members aren’t listed.