Trench etching process for photoresist line roughness improvement
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., Tsmc Nanjing Company, Limited
InventorsSheng-Lin HSIEH, I-Chih CHEN, Ching-Pei HSIEH, Kuan Jung CHEN
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Abstract
A semiconductor device includes a substrate. The semiconductor device further includes a conductive structure in the substrate. The semiconductor device further includes an etch stop layer over the substrate. The semiconductor device further includes an interlayer dielectric (ILD) over the etch stop layer. The semiconductor device further includes a dual damascene conductive element in the ILD, wherein the dual damascene conductive element extends through the etch stop layer to electrically connect to the conductive structure, and the dual damascene conductive element has a line end roughness (LER) ranging from 3.3 nanometers (nm) to 5.3 nm.
Claims20
A semiconductor device comprising:
- a substrate;
- a dielectric layer over the substrate;
- and
- a conductive line in the dielectric layer, wherein the conductive line has a line end roughness (LER) ranging from 3.3 nanometers (nm) to 5.3 nm.
A semiconductor device comprising:
- a substrate;
- a conductive structure in the substrate;
- an etch stop layer over the substrate;
- an interlayer dielectric (ILD) over the etch stop layer;
- and
- a dual damascene conductive element in the ILD, wherein the dual damascene conductive element extends through the etch stop layer to electrically connect to the conductive structure, and the dual damascene conductive element has a line end roughness (LER) ranging from 3.3 nanometers (nm) to 5.3 nm.
A semiconductor device comprising:
- a substrate;
- a conductive structure in the substrate;
- an etch stop layer over the substrate;
- an interlayer dielectric (ILD) over the etch stop layer;
- a first hardmask layer over the ILD;
- a second hardmask layer over the first hardmask layer;
- and
- a dual damascene conductive element, wherein the dual damascene conductive element extends through the first hardmask layer, the second hardmask layer, the ILD and the etch stop layer to electrically connect to the conductive structure, and the dual damascene conductive element has a line end roughness (LER) ranging from 3.3 nanometers (nm) to 5.3 nm.
Dependencies are inferred from the claim text.