Single-photon avalanche diode structure and manufacturing process

A photodetector, comprising:

• a semiconductor substrate;
• a mesa on the semiconductor substrate;
• a diode having an absorption region in the mesa;
• a first electrode contact plug for the diode, wherein the first electrode contact plug lands on top of the mesa;
• a second electrode contact plug for the diode, wherein the second electrode contact plug passes through a dielectric structure and lands on the semiconductor substrate to one side of the mesa, wherein the dielectric structure comprises an interlevel dielectric, which is silicon dioxide (SiO2) or a low k dielectric, and a plurality of second-type dielectric layers, which each comprise one or another of aluminum oxide (AlOx), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), or silicon oxycarbonitride (SiOCN);
• and
• a light-blocking grid over the semiconductor substrate, wherein the light-blocking grid passes through the plurality of second-type dielectric layers and lands on another second-type dielectric layer which comprises one of aluminum oxide (AlOx), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SIOC), or silicon oxycarbonitride (SiOCN).

A method of manufacturing a photodetector, the method comprising:

• providing a semiconductor body having a front side and a back side;
• forming a p-n junction in the semiconductor body;
• epitaxially growing a second semiconductor on the front side of the semiconductor body;
• patterning the second semiconductor, wherein patterning leaves a mesa comprising the second semiconductor over the p-n junction;
• doping the semiconductor body in an area to one side of the mesa, wherein doping forms a first contact region in the semiconductor body;
• depositing a first oxide layer;
• depositing a lower etch stop layer over the first oxide layer;
• pattering the lower etch stop layer, wherein patterning removes the lower etch stop layer from an area over the first contact region;
• depositing a second oxide layer;
• depositing an upper etch stop layer over the second oxide layer;
• forming an interlevel dielectric layer over the upper etch stop layer;
• forming a mask over the interlevel dielectric layer, wherein the mask has a first opening over the first contact region and a second opening in the shape of a grid;
• etching through the mask, wherein etching forms a first hole corresponding to the first opening and trenches corresponding to the second opening;
• and
• depositing metal, wherein the metal fills the first hole to form a first electrode contact plug and fills the trenches to form a light-blocking grid, wherein the light-blocking grid is spaced over semiconductor body and the first electrode contact plug is in or on the semiconductor body and is coupled to the first contact region.