Analog in-sensor vision processing arrays
AssigneeUniversity of Massachusetts
InventorGuangyu Xu
Life of this patent
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Abstract
Scalable in-sensor visual processing arrays of dual-gate amorphous-silicon photodiodes, which are used for multiplexed event sensing at sub-ms precision and edge detection of multiple objects, respectively. Both arrays are built in ca. 200-μm pitches and consume zero static power via their bias conditions; their analog output directly captures the amplitude of event-driven light changes and light intensities on the object edges without complex digitization circuits. Capable of processing both temporal and spatial visual information, these arrays emulate the signaling pathways in the human retina, suggesting a path towards large-scale analog in-sensor visual processing systems.
Claims22
A computer vision system, comprising:
- a first scalable in-sensor visual processing array configured and arranged for event sensing;
- and
- a second scalable in-sensor visual processing array configured and arranged for edge detection.
A computing unit for an in-sensor visual processing array, comprising:
- a first gate:
- a first photodiode;
- a first resistor;
- a first capacitor;
- the first resistor and first capacitor monolithically built together with, and electrically connected to, the first photodiode in parallel.
An in-sensor computer vision system, comprising:
- a plurality of computing units, comprising dual-gate amorphous-silicone photodiodes;
- the computing units configured and arranged in a grid pattern.
A method of making an in-sensor computer vision system, via deposition and etching techniques, comprising:
- forming a silicon-based substrate;
- forming photodiode gate routing lines on the substrate;
- depositing a passivation layer over the gate routing lines and substrate;
- etching vias through the passivation layer to form contact placement areas;
- forming gate contacts on the contact placement areas, making connections to the gate routing lines;
- depositing a gate oxide layer to form a capacitor;
- etching α-Si areas over the gate routing lines to form light absorbing regions for the photodiode;
- and
- forming S and D contacts on the gate routing lines of the photodiode via etching and metallization;
- whereby a computing unit is formed.
Dependencies are inferred from the claim text.